High-speed operation of a 64-bit circular shift register

Herr, A.M.; Mancini, C.A.; Vukovic, N.; Bocko, Mark F.; Feldman, M.J.

doi:10.1109/77.712142

Cited by 11 publications

(4 citation statements)

References 10 publications

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“…The ring oscillator and prescaler sections were assembled using cells that were already designed, fabricated and tested for previous designs [4]. The circuit parameters of these cells are optimized for maximum yield [5] according to parametervariation data supplied by the foundry service.…”

Section: Circuit Layout and Fabricationmentioning

confidence: 99%

Phase-locked operation of RSFQ ring oscillators

Mancini¹,

Bocko²

1999

Supercond. Sci. Technol.

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Ring oscillators are the traditional on-chip clock source for RSFQ mixed-signal and digital circuits. Their long-term frequency stability is essential for certain signal processing applications such as the sampling clock for an A/D converter or the output clock of a D/A converter. However conventional bias schemes lead to excessive drift in the frequency. Embedding the ring oscillator in a phase-locked loop (PLL) circuit allows it to inherit the frequency stability of an external reference source. An RSFQ circuit comprised of a ring oscillator, a divide-by-220 prescaler and a resynchronizer D flip-flop was fabricated using the standard 1 kA cm-2 niobium foundry service from Hypres. The circuit was stabilized using a low-frequency PLL with a bandwidth of 6 Hz. The output of the phase detector in the PLL was used to produce a feedback current that stabilized the frequency of the ring oscillator at around 8 GHz. The frequency spectrum of the RSFQ scaled oscillator output was measured in open- and closed-loop configurations. Compared to the open-loop phase noise spectrum the closed-loop spectrum showed a decrease of 30 dB of the oscillator phase noise at an offset of 1 Hz from the divided-down carrier frequency of 4.1 kHz. This agreed with the classical phase-locked loop model for the system. The long-term frequency drift of the RSFQ clock was determined by the stability of the oven-controlled quartz oscillator used as the reference in the PLL.

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Section: Circuit Layout and Fabricationmentioning

confidence: 99%

Phase-locked operation of RSFQ ring oscillators

Mancini¹,

Bocko²

1999

Supercond. Sci. Technol.

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“…When compared to semiconductor technology, rapid single flux quantum (RSFQ) circuits have the advantages of higher speed and reduced power consumption [1]. Next-generation high-performance computing [2][3][4][5], in which core processor circuits process constant streams of data at several tens of gigahertz [6][7][8][9][10][11][12], is one of the most promising uses of RSFQ technology. Demonstrating the long-term stability of the RSFQ circuit operating at high frequencies is critical for research and development toward real-world applications.…”

Section: Introductionmentioning

confidence: 99%

On-chip test vector generation and downsampling for testing RSFQ circuits

Chen¹,

Ying²,

Ren³

et al. 2022

Supercond. Sci. Technol.

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An on-chip high-frequency testing method for rapid single flux quantum (RSFQ) circuits is proposed. This method employs test vectors based on pseudo-random sequences created by an on-chip high-frequency clock generator (CG) and a linear feedback shift register with parallel outputs (LSPO). Downsamplers (DSMs) at the outputs of a circuit under test (CUT) decimate the CUT output data so that high-frequency testing can be performed at sufficiently low data rates between the CUT and room-temperature electronics. The proposed testing can continuously test the circuit at high frequency with low-cost instruments. All of the critical subsystems, including LSPO, CG, and DSM, were designed, fabricated, and successfully tested. We validated proper operation at up to 40 GHz, confirming the concept and execution.

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“…Most of these circuits have been based on Rapid Single Flux Quantum (RSFQ) logic, in which the information is carried in the presence or absence of single-flux-quantum (SFQ) voltage pulses generated by damped Josephson junctions [4]- [6]. The industry standard has been based on a rather modest 3-µm linewidth; even so, complex Nb RSFQ circuits operating (in liquid helium at 4.2 K) at clock speeds in excess of 20 GHz have become routine [7]- [10]. Furthermore, scaling to smaller dimensions should yield dramatic increases in speed and circuit density.…”

Section: Introductionmentioning

confidence: 99%

Can RSFQ logic circuits be scaled to deep submicron junctions?

Kadin

Mancini

Feldman

et al. 2001

IEEE Trans. Appl. Supercond.

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Scaling of niobium RSFQ integrated circuit technology to deep submicron dimensions (linewidths of 300 nm or less) should permit increased clock rate (up to 250 GHz) and increased areal density of Josephson junctions (up to 1 million junctions/cm 2 ), without the need for external shunt resistors. It is shown how existing circuit layouts can be scaled down to these dimensions, while maintaining the precise timing essential for correct operation. Additional issues related to the practical realization of such circuits are discussed, including effects of selfheating and models for the generation and propagation of sub-ps single-flux-quantum pulses.

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High-speed operation of a 64-bit circular shift register

Cited by 11 publications

References 10 publications

Phase-locked operation of RSFQ ring oscillators

Phase-locked operation of RSFQ ring oscillators

On-chip test vector generation and downsampling for testing RSFQ circuits

Can RSFQ logic circuits be scaled to deep submicron junctions?

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