X-ray imaging is a widely used imaging modality in the medical diagnostic field due to its availability, low cost, high spatial resolution, and fast image acquisition. X-ray photons in standard X-ray sources are polychromatic. Detectors that allow to extract the "color" information of the individual X-rays can lead to contrast enhancement, improved material identification or reduction of beam hardening artifacts at the system level, if we compare them with the widely spread energy integrating detectors. Today, in the field of computed tomography (CT), prototypes of clinical grade systems based on spectral photon counting detectors are currently available for clinical research from different companies. One of the key system components in that development is the X-ray photon detector. This article reviews the photon detection hardware, from the conversion of X-rays into electrical signals to the pulse processing electronics. A review of available photon counting application specific integrated circuits (ASICs) for spectroscopic X-ray imaging is presented with emphasis on the CT medical imaging application.
A: Depleted monolithic active pixel sensors (DMAPS), which exploit high voltage and/or high resistivity add-ons of modern CMOS technologies to achieve substantial depletion in the sensing volume, have proven to have high radiation tolerance towards the requirements of ATLAS in the high-luminosity LHC era. Depleted fully monolithic CMOS pixels with fast readout architectures are currently being developed as promising candidates for the outer pixel layers of the future ATLAS Inner Tracker, which will be installed during the phase II upgrade of ATLAS around year 2025. In this work, two DMAPS prototype designs, named LF-MonoPix and TJ-MonoPix, are presented. LF-MonoPix was designed and fabricated in the LFoundry 150 nm CMOS technology, and TJ-MonoPix has been designed in the TowerJazz 180 nm CMOS technology. Both chips employ the same readout architecture, i.e. the column drain architecture, whereas different sensor implementation concepts are pursued. The design of the two prototypes will be described. First measurement results for LF-MonoPix will also be shown.
K: Depleted monolithic CMOS pixels, particle tracking detectors (solid-state detectors), Front-end electronics for detector readout, VLSI circuit 1Corresponding author.
Power consumption is always a concern in the design of readout chips for hybrid pixel detectors. The Timepix3 chip is capable of dealing with up to 80 Mhits/cm 2 /sec and tagging each hit within a time bin of 1.56 ns. At full speed the Timepix3 chip will consume 1.3 W. We consider how to reduce power consumption if hit rate and/or time stamp precision is not important. The analog power can be reduced by more than an order of magnitude with little impact on noise by reducing the bias current of the input transistor and increasing the return to zero time of the preamplifier. Digital power consumption might be ∼ 6× lower by reducing the clock frequency to 1 MHz from the nominal 40 MHz. Simulations and measurements are presented. In very low power mode Timepix3 could consume only ∼150 mW on 2 cm 2 .The new Timepix4 chip aims at time tagging within a bin of 200 psec. Propagation of a 5 GHz clock around the pixel matrix would be impractical. We present a novel architecture implementing a very low jitter clock to the full pixel matrix. A digital Delay Locked Loop is designed in which the delay chain is distributed along the two columns of each super-pixel with the phase comparator and control located at the base of the double column. The control system locks all super-pixels to the low jitter (<100 ps) global 40 MHz clock. Simulations show that this can be achieved with a power consumption of only 25 mW/cm 2 while preserving high rate capability.
A novel monolithic pixelated sensor and readout chip, the CLIC Tracker Detector (CLICTD) chip, is presented. The CLICTD chip was designed targeting the requirements of the silicon tracker development for the experiment at the Compact Linear Collider (CLIC), and has been fabricated in a modified 180 nm CMOS imaging process with charge collection on a high-resistivity p-type epitaxial layer. The chip features a matrix of 16×128 elongated channels, each measuring 300×30 µm 2. Each channel contains 8 equidistant collection electrodes and analog readout circuits to ensure prompt signal formation. A simultaneous 8-bit Time-of-Arrival (with 10 ns time bins) and 5-bit Time-over-Threshold measurement is performed on the combined digital output of the 8 sub-pixels in every channel. The chip has been fabricated in two process variants and characterised in laboratory measurements using electrical test pulses and radiation sources. Results show a minimum threshold between 135 and 180 e − and a noise of about 14 e − RMS. The design aspects and characterisation results of the CLICTD chip are presented.
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