Study of low power front-ends for hybrid pixel detectors with sub-ns time tagging

Llopart, X.; Alozy, J.; Ballabriga, R.; Campbell, M.; Egidos, N.; Fernandez, J.M.; Heijne, E.; Kremastiotis, I.; Santin, E.; Tlustos, L.; Sriskaran, Viros; Poikela, T.

doi:10.1088/1748-0221/14/01/c01024

Cited by 16 publications

(18 citation statements)

References 3 publications

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“…It can be depicted in Fig.8 and Fig .9 that the most dominant component of the ENC noise is the thermal noise component. Thus, if the device operates in a low count rate environment, substantial reductions in power consumption can be obtained with little or no noise penalty by reducing the bias current of the input transistor provided a good separation between the preamplifier rise and fall time is ensured [25]. The transient response of CSA is shown in Fig.10 and Fig.11.…”

Section: Resultsmentioning

confidence: 99%

A 0.35μm Low-Noise Stable Charge Sensitive Amplifier for Silicon Detectors Applications

Bhuiyan¹

2020

Informacije MIDEM

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The Charge Sensitive Amplifier (CSA) is the key module of the front-end electronics of various types of Silicon detectors and most radiation detection systems. High gain, stability, and low input noise are the major concerns of a typical CSA circuit in order to achieve amplified susceptible input charge (current) for further processing. To design such a low-noise, stable, and low power dissipation solution, a CSA is required to be realized in a complementary metal-oxide-semiconductor (CMOS) technology with a compact design. This research reports a low-noise highly stabile CSA design for Silicon detectors applications, which has been designed and validated in TSMC 0.35 um CMOS process. In a typical CSA design, the detector capacitance and the input transistor's width are the dominant parameters for achieving low noise performance. Therefore, the Equivalent Noise Charge (ENC) with respect to those parameters has been optimized, for a range of detector capacitance from 0.2 pF-2 pF. However, the parallel noise of the feedback was removed by adopting a voltage-controlled NMOS resistor, which in turn helped to achieve high stability of the circuit. The simulation results provided a baseline gain of 9.92 mV/fC and show that ENC was found to be 42.5 e-with 3.72 e-/pF noise slope. The Corner frequency exhibited by the CSA is 1.023 GHz and the output magnitude was controlled at-56.8 dB; it dissipates 0.23 mW with a single voltage supply of 3.3 V with an active die area of 0.0049 mm 2 .

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Section: Resultsmentioning

confidence: 99%

A 0.35μm Low-Noise Stable Charge Sensitive Amplifier for Silicon Detectors Applications

Bhuiyan¹

2020

Informacije MIDEM

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“…As a rundown, in Table 3 the general highlights of the FEE circuit are presented. To achieve a high signal-to-noise ratio (SNR) and reduce power consumption, ENC, and active die area of the chip, the configurations presented in the literature have been consulted [ 6 , 14 , 16 , 20 , 22 , 24 , 39 , 52 , 53 , 54 , 55 , 56 ]. Considering the critical contrast on the input transistor’s capacitance, the outcomes are empowering.…”

Section: Simulation Outcomes and Discussionmentioning

confidence: 99%

“…The following FOM was defined to highlight the performances of this design with recently published works [ 53 , 54 , 55 , 56 ]. This parameter can be explained as the speed-sensitivity product to the power dissipation for a given sensor capacitance.…”

Section: Simulation Outcomes and Discussionmentioning

confidence: 99%

“…Process variations outcomes worsen with reducing the channel length [ 52 , 53 ]. Mismatch being a function of threshold voltage (VTH) and supply voltage (VDD), low VTH (LVT) transistors have a reduced mismatch impact due to higher VDD/VTH ratio than standard VTH (SVT) or high VTH (HVT) transistors; the proportionate change in temperature from SVT to HVT is much larger as compared to that from LVT to SVT [ 54 , 56 , 57 ]. Thus, it is more advantageous to move from HVT transistors to SVT devices, but this results in high power dissipation.…”

Section: Simulation Outcomes and Discussionmentioning

confidence: 99%

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An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

Jérôme

Evariste

Bernard

et al. 2021

Sensors

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The front-end electronics (FEE) of the Compact Muon Solenoid (CMS) is needed very low power consumption and higher readout bandwidth to match the low power requirement of its Short Strip application-specific integrated circuits (ASIC) (SSA) and to handle a large number of pileup events in the High-Luminosity Large Hadron Collider (LHC). A low-noise, wide bandwidth, and ultra-low power FEE for the pixel-strip sensor of the CMS has been designed and simulated in a 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process. The design comprises a Charge Sensitive Amplifier (CSA) and a fast Capacitor-Resistor-Resistor-Capacitor (CR-RC) pulse shaper (PS). A compact structure of the CSA circuit has been analyzed and designed for high throughput purposes. Analytical calculations were performed to achieve at least 998 MHz gain bandwidth, and then overcome pileup issue in the High-Luminosity LHC. The spice simulations prove that the circuit can achieve 88 dB dc-gain while exhibiting up to 1 GHz gain-bandwidth product (GBP). The stability of the design was guaranteed with an 82-degree phase margin while 214 ns optimal shaping time was extracted for low-power purposes. The robustness of the design against radiations was performed and the amplitude resolution of the proposed front-end was controlled at 1.87% FWHM (full width half maximum). The circuit has been designed to handle up to 280 fC input charge pulses with 2 pF maximum sensor capacitance. In good agreement with the analytical calculations, simulations outcomes were validated by post-layout simulations results, which provided a baseline gain of 546.56 mV/MeV and 920.66 mV/MeV, respectively, for the CSA and the shaping module while the ENC (Equivalent Noise Charge) of the device was controlled at 37.6 e− at 0 pF with a noise slope of 16.32 e−/pF. Moreover, the proposed circuit dissipates very low power which is only 8.72 µW from a 3.3 V supply and the compact layout occupied just 0.0205 mm2 die area.

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“…As a result, it cannot be ensured that the clock will arrive distributed during one period to the different sinks, which might lead to PSIJ; and the timestamp error associated with the CDN can only be bound at a local level. These nonidealities are prevented in the Timepix4 pixel detector [16]: the CDN branches consist of digital DLLs (dDLLs) and local clock trees to distribute a 40-MHz master clock across an area of close to 7 cm 2 with a skew in the order of 100 ps. Digital low-pass filtering is used to reduce the impact of jitter.…”

Section: Toward a Proposal Of Cdn Architecturementioning

confidence: 99%

20-ps Resolution Clock Distribution Network for a Fast-Timing Single-Photon Detector

Egidos

Ballabriga

Bandi

et al. 2021

IEEE Trans. Nucl. Sci.

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The time resolution of active pixel sensors whose timestamp mechanism is based on time-to-digital converters is critically linked to the accuracy in the distribution of the master clock signal that latches the timestamp values across the detector. The clock distribution network (CDN) that delivers the master clock signal must compensate process-voltage-temperature variations to reduce static time errors (skew) and minimize the power supply bounce to prevent dynamic time errors (jitter). To achieve sub-100-ps time resolution within pixel detectors and thus enable a step forward in multiple imaging applications, the network latencies must be adjusted in steps well below that value. Power consumption must be kept as low as possible. In this work, a selfregulated CDN that fulfills these requirements is presented for the FastICpix single-photon detector aiming at a 65-nm process. A 40-MHz master clock is distributed to 64 × 64 pixels over an area of 2.4 × 2.4 cm 2 using digital delay-locked loops, achieving clock leaf skew below 20 ps with a power consumption of 26 mW. Guidelines are provided to adapt the system to arbitrary chip area and pixel pitch values, yielding a versatile design with very fine time resolution.

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Study of low power front-ends for hybrid pixel detectors with sub-ns time tagging

Cited by 16 publications

References 3 publications

A 0.35μm Low-Noise Stable Charge Sensitive Amplifier for Silicon Detectors Applications

A 0.35μm Low-Noise Stable Charge Sensitive Amplifier for Silicon Detectors Applications

An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

20-ps Resolution Clock Distribution Network for a Fast-Timing Single-Photon Detector

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