In this paper the three main hardware architectures for the two-dimensional discrete wavelet transform (2D-DWT) are reviewed. Also optimization techniques applicable to all three architectures are described. The main contribution of this work is the quantitative comparison among these design alternatives for the 2D-DWT. The comparison is performed in terms of memory requirements, throughput, and energy dissipation, and is based on a theoretical analysis of the alternative architectures and schedules. Memory requirements, throughput, and energy are expressed by analytical equations with parameters from both the 2D-DWT algorithm and the implementation platform. The parameterized equations enable the early but efficient exploration of the various trade-off related to the selection to the one or the other architecture.

No abstract

No abstract

No abstract

No abstract