Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications

Soudris, Dimitrios; Zervas, N.D.; Argyriou, Antonios; Dasygenis, Minas; Tatas, K.; Goutis, C.E.; Thanailakis, A.

doi:10.1007/3-540-45373-3_26

Cited by 30 publications

(19 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Landman's energy model has been used in [6], [14], [21], which is parameterized by the capacitances and the frequencies of read and write operations. Several power models exist for cache [5], which are based on the estimate of the cache line hit rate and several hardware-related parameters.…”

Section: Proposed Power Modelmentioning

confidence: 99%

“…Brockmeyer et al [13] refine the memory assignment and placement involved in [6] with the low energy objective. The effects of different combinations of data reuse transformations and memory system structures on the system power consumption and performance have been shown in [14] and [15] for platforms with multiple embedded instruction set processors.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems

Liu

Constantinides

Masselos

et al. 2009

IET Comput. Digit. Tech.

View full text Add to dashboard Cite

Contemporary FPGA-based reconfigurable systems have been widely used to implement data dominated applications. In these applications data transfer and storage consume a large proportion of the system energy. Exploiting data reuse can introduce significant power savings, but also introduces the extra requirement for on-chip memory. To aid data reuse design exploration early during the design cycle, we present an optimization approach to achieve a power-optimal design satisfying an on-chip memory constraint in a targeted FPGA-based platform. The data reuse exploration problem is mathematically formulated and shown to be equivalent to the Multiple-Choice Knapsack Problem (MCKP). The solution to this problem for an application code corresponds to the decision of which array references are to be buffered on-chip and where loading reused data of the array references into on-chip memory happens in the code, in order to minimize power consumption for a fixed on-chip memory size. We also present an experimentally verified power model, capable of providing the relative power information between different data reuse design options of an application, resulting in a fast and efficient design space exploration. The experimental results demonstrate that the approach enables us to find the most power efficient design for all the benchmark circuits tested.

show abstract

Section: Proposed Power Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems

Liu

Constantinides

Masselos

et al. 2009

IET Comput. Digit. Tech.

View full text Add to dashboard Cite

show abstract

“…The transfer and storage of data are significant sources of power consumption in custom computations [2], so warrant specific attention. In the preceding system, Sonic, data transfer is systolic; each clock cycle one pixel value is clocked into the engine, and one is clocked out.…”

Section: Data Transfer and Storagementioning

confidence: 99%

“…-Minimising power consumed in data transmission and data reuse, the two most important factors in low-power design of custom computational platforms [2].…”

Section: Introductionmentioning

confidence: 99%

A Reconfigurable Platform for Real-Time Embedded Video Image Processing

Sedcole

Cheung

Constantinides

et al. 2003

Field Programmable Logic and Application

View full text Add to dashboard Cite

Abstract. The increasing ubiquity of embedded digital video capture creates demand for high-throughput, low-power, flexible and adaptable integrated image processing systems. An architecture for a system-ona-chip solution is proposed, based on reconfigurable computing. The inherent system modularity and the communication infrastructure are targeted at enhancing design productivity and reuse. Power consumption is addressed by a combination of efficient streaming data transfer and reuse mechanisms. It is estimated that the proposed system would be capable of performing up to ten complex image manipulations simultaneously and in real-time on video resolutions up to XVGA.

show abstract

“…Second, applications are often split into multiple tasks running concurrently, either to improve the power dissipation [32] or performance [36]. Third, SoCs are evolving in the direction of distributed-memory architectures, offering high throughput and low latency [22,39], coupled with a low power consumption [23]. Fourth, address-less streaming communication between IPs is growing in importance to alleviate contention for shared memories and is becoming a key aspect in achieving efficient parallel processing [18,40].…”

Section: Introductionmentioning

confidence: 99%

An on-chip interconnect and protocol stack for multiple communication paradigms and programming models

Hansson

Goossens

2009

Proceedings of the 7th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis

View full text Add to dashboard Cite

A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The diverse requirements, coupled with the IPs being developed by unrelated design teams, lead to multiple communication paradigms, programming models, and interface protocols that the on-chip interconnect must accommodate.Traditionally, on-chip buses offer distributed shared memory communication with established memory-consistency models, but are tightly coupled to a specific interface protocol. On-chip networks, on the other hand, offer layering and interface abstraction, but are centred around point-topoint streaming communication, and do not address issues at the higher layers in the protocol stack, such as memoryconsistency models and message-dependent deadlock.In this work we introduce an on-chip interconnect and protocol stack that combines streaming and distributed shared memory communication. The proposed interconnect offers an established memory-consistency model and does not restrict any higher-level protocol dependencies. We present the protocol stack and the architectural blocks and quantify the cost, both on the block level and for a complete SoC. For a multi-processor multi-application SoC with multiple communication paradigms and programming models, our proposed interconnect occupies only 4% of the chip area.

show abstract

Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications

Cited by 30 publications

References 6 publications

Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems

Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems

A Reconfigurable Platform for Real-Time Embedded Video Image Processing

An on-chip interconnect and protocol stack for multiple communication paradigms and programming models

Contact Info

Product

Resources

About