Power exploration of multimedia applications realized on embedded cores

Zervas, N.D.; Masselos, K.; Koufopavlou, O.; Goutis, C.E.

doi:10.1109/iscas.1999.780021

Cited by 10 publications

(13 citation statements)

References 10 publications

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“…It is taken further and oriented towards predefined memory organization in [7]. The authors in [8,9] study the effects of data reuse decisions on power, performance and area in embedded processing systems. The effect of data reuse transformations on a general purpose processor has been explored in [10].…”

Section: Related Workmentioning

confidence: 99%

Energy Efficiency Effects of Vectorization in Data Reuse Transformations for Many-Core Processors—A Case Study †

Hasib

Natvig

Kjeldsberg

et al. 2017

JLPEA

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Abstract:Thread-level and data-level parallel architectures have become the design of choice in many of today's energy-efficient computing systems. However, these architectures put substantially higher requirements on the memory subsystem than scalar architectures, making memory latency and bandwidth critical in their overall efficiency. Data reuse exploration aims at reducing the pressure on the memory subsystem by exploiting the temporal locality in data accesses. In this paper, we investigate the effects on performance and energy from a data reuse methodology combined with parallelization and vectorization in multi-and many-core processors. As a test case, a full-search motion estimation kernel is evaluated on Intel R Core TM i7-4700K (Haswell) and i7-2600K (Sandy Bridge) multi-core processors, as well as on an Intel R Xeon Phi TM many-core processor (Knights Landing) with Streaming Single Instruction Multiple Data (SIMD) Extensions (SSE) and Advanced Vector Extensions (AVX) instruction sets. Results using a single-threaded execution on the Haswell and Sandy Bridge systems show that performance and EDP (Energy Delay Product) can be improved through data reuse transformations on the scalar code by a factor of ≈3× and ≈6×, respectively. Compared to scalar code without data reuse optimization, the SSE/AVX2 version achieves ≈10×/17× better performance and ≈92×/307× better EDP, respectively. These results can be improved by 10% to 15% using data reuse techniques. Finally, the most optimized version using data reuse and AVX512 achieves a speedup of ≈35× and an EDP improvement of ≈1192× on the Xeon Phi system. While single-threaded execution serves as a common reference point for all architectures to analyze the effects of data reuse on both scalar and vector codes, scalability with thread count is also discussed in the paper.

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Section: Related Workmentioning

confidence: 99%

Energy Efficiency Effects of Vectorization in Data Reuse Transformations for Many-Core Processors—A Case Study †

Hasib

Natvig

Kjeldsberg

et al. 2017

JLPEA

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show abstract

“…In this paper, we assume that the on-chip power is closely related to the SRAM capacity (i.e. word-length Â # of words) [16]. Therefore, the simplified power described by Eq.…”

Section: Data Localitymentioning

confidence: 99%

Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead

Liu¹,

Lee²

2007

J Sign Process Syst Sign Image

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Abstract. This paper describes a novel memory hierarchy and line-pixel-lookahead (LPL) for an H.264/AVC video decoder. The memory system is the bottleneck of most video processors, particularly in the newly announced H.264/AVC. This is because it utilizes the neighboring pixels to create a reliable predictor, leading to a dependency on a long past history of data. This problem can be resolved by allocating memory space but inducing large silicon area and power consumption as well. We first review the existing solutions and propose a three-level memory hierarchy with line-pixel-lookahead to improve access efficiency. Three-level memory hierarchy includes registers, content/slice SRAM and external frame DRAM. We emphasize the need to consider the secondary hierarchy, content/slice SRAM, during the design of an H.264/AVC decoder. Specifically, we introduce a slice SRAM and line-pixel-lookahead to lower the memory capacity and external bandwidth. This SRAM stores neighboring pixels and prevents the data re-access from DRAM. Linepixel-lookahead exploits multi-dimensional pixel locality so as to averagely improve prediction performance by 6.54% compared to conventional vertical prediction. Simulation results also reveal that the proposal makes a better trade-off between memory allocation and external bandwidth as well as power, leading to 50% of memory power reduction compared to the design without exploiting the secondary slice SRAM hierarchy.

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“…The application of the existing methodology [ 11 for the Data Transfer and Storage Exploration (DTSE) step, including its extension for the case of embedded processor cores as proposed by [4], [6] requires the evaluation of each code transformation by executing the corresponding code on a simulator, such as the M u l a t o r [7]. This process can be extremely time consuming, leading to prohibitive requirements in terms of time and effort.…”

Section: Design Exploration: An Analytical Approachmentioning

confidence: 99%

“…However, instruction related power consumption is not taken into account since only custom architectures are considered. In [4] it was illustrated that the instruction memory power consumption in embedded programmable processors cannot be negIected since in most cases is larger than the power consumed in the data memory hierarchy.…”

Section: Introductionmentioning

confidence: 99%

“…All previous work adopt a simulative approach in order to determine the optimal solution from a pool of possible implementations which is the end result of the data-reuse exploration and decision methodology [4]. Each alternative has to be implemented, compiled and executed on a processor simulator in order to evaluate its power efficiency.…”

Section: Introductionmentioning

confidence: 99%

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Power reduction for multimedia applications through data-reuse memory exploration

Kougia

Chatzigeorgiou²,

Nikolaidis³

ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)

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Power consumption of multimedia applications executing on embedded cores is heavily dependent on data transfers between system memory and processing units. In this paper, a power optimizing methodology based on data-reuse decisions and the development of a custom memory hierarchy is extended in order to determine the optimal solution in a rapid and reliable way. Data-reuse transformations are applied on a typical motion estimation algorithm in order to reduce the data-related power consumption by moving background memory accesses to smaller foreground memories, which are less power costly. Fast exploration of the design space is achieved by extracting analytical expressions for the number of accesses to data and instruction memories.

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Power exploration of multimedia applications realized on embedded cores

Cited by 10 publications

References 10 publications

Energy Efficiency Effects of Vectorization in Data Reuse Transformations for Many-Core Processors—A Case Study †

Energy Efficiency Effects of Vectorization in Data Reuse Transformations for Many-Core Processors—A Case Study †

Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead

Power reduction for multimedia applications through data-reuse memory exploration

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