Diverse diode characteristics were observed in two-dimensional (2D) black phosphorus (BP) and molybdenum disulfide (MoS) heterojunctions. The characteristics of a backward rectifying diode, a Zener diode, and a forward rectifying diode were obtained from the heterojunction through thickness modulation of the BP flake or back gate modulation. Moreover, a tunnel diode with a precursor to negative differential resistance can be realized by applying dual gating with a solid polymer electrolyte layer as a top gate dielectric material. Interestingly, a steep subthreshold swing of 55 mV/dec was achieved in a top-gated 2D BP-MoS junction. Our simple device architecture and chemical doping-free processing guaranteed the device quality. This work helps us understand the fundamentals of tunneling in 2D semiconductor heterostructures and shows great potential in future applications in integrated low-power circuits.

Currently 2D crystals are being studied intensively for use in future nano-electronics, as conventional semiconductor devices face challenges in high power consumption and short channel effects when scaled to the quantum limit. Toward this end, achieving barrier-free contact to 2D semiconductors has emerged as a major roadblock. In conventional contacts to bulk metals, the 2D semiconductor Fermi levels become pinned inside the bandgap, deviating from the ideal Schottky-Mott rule and resulting in significant suppression of carrier transport in the device. Here we realized MoS 2 polarity control without extrinsic doping by employing 1D elemental metal contact scheme. Use of high work function palladium (Pd) or gold (Au) achieved high quality p-type dominant contact to intrinsic MoS 2 , realizing Fermi level de-pinning. Field-effect transistors (FET) with Pd edge contact and Au edge contact show high performance with the highest hole mobility reaching 330 cm 2 /Vs and 432 cm 2 /Vs at 300 K respectively. The ideal Fermi level alignment allows creation of p-and n-type FETs on the same intrinsic MoS 2 flake using Pd and low work function molybdenum (Mo) contacts, respectively. This device acts as an efficient inverter, a basic building block for semiconductor integrated circuits, with gain reaching 15 at V D =5 V.

A novel algorithm is proposed for robust step detection irrespective of step mode and device pose in smartphone usage environments. The dynamics of smartphones are decoupled into a peak-valley relationship with adaptive magnitude and temporal thresholds. For extracted peaks and valleys in the magnitude of acceleration, a step is defined as consisting of a peak and its adjacent valley. Adaptive magnitude thresholds consisting of step average and step deviation are applied to suppress pseudo peaks or valleys that mostly occur during the transition among step modes or device poses. Adaptive temporal thresholds are applied to time intervals between peaks or valleys to consider the time-varying pace of human walking or running for the correct selection of peaks or valleys. From the experimental results, it can be seen that the proposed step detection algorithm shows more than 98.6% average accuracy for any combination of step mode and device pose and outperforms state-of-the-art algorithms.

Effective control of 2D transistors polarity is a critical challenge in the process for integrating 2D materials into semiconductor devices. Herein, a doping‐free approach for developing tungsten diselenide (WSe2) logic devices by utilizing the van der Waals (vdWs) bottom electrical contact with platinum and indium as the high and low work function metal respectively is reported. The device structure is free from chemical disorder and crystal defects arising from metal deposition, which enables a near ideal Fermi‐level de‐pinning. With effective controllability of device polarity through metal work function change, a complementary metal‐oxide‐semiconductor field effect transistor inverter with a gain of 198 at a bias voltage of 4.5 V is achieved. This study demonstrates an ultrahigh performance 2D inverter realized by controlling the device polarity from using Fermi‐level pinning‐free vdWs bottom contacts.

Highly doped graphene holds promise for next-generation electronic and photonic devices.However, chemical doping cannot be precisely controlled, and introduces external disorder that significantly diminishes the carrier mobility and therefore the graphene conductivity. Here, we show that monolayer tungsten oxyselenide (TOS) created by oxidation of WSe2 acts as an efficient and low-disorder hole-dopant for graphene. When the TOS is directly in contact with graphene, the induced hole density is 3 × 10 13 cm -2 , and the room-temperature mobility is 2,000 cm 2 /V•s, far exceeding that of chemically-doped graphene. Inserting WSe2 layers between the TOS and graphene tunes the induced hole density as well as reduces charge disorder such that the mobility exceeds 20,000 cm 2 /V•s and reaches the limit set by acoustic phonon scattering, resulting in sheet resistance below 50 /□. An electrostatic model based on work-function mismatch accurately describes the tuning of the carrier density with WSe2 interlayer thickness. These films show unparalleled performance as transparent conductors at telecommunication wavelengths, as shown by measurements of transmittance in thin films and insertion loss in photonic ring resonators. This work opens up new avenues in optoelectronics incorporating two-dimensional heterostructures including infrared transparent conductors, electro-phase modulators, and various junction devices.

WSe2 FET oxidized by plasma. Channel resistance decreases exponentially with increasing WSe2 work function, approaching thermal limit.

devices, which can accommodate various materials via stacking. With respect to future applications, WSe 2 exhibits strong potential to be used in field-effect transistors (FETs), photodetectors, light-emitting diodes, and solar cells. [5-9] The metal-semiconductor (MS) interface is a critical factor influencing the electronic performance of 2D WSe 2 devices in that it is strongly correlated to device polarity. [10] Thus, the Schottky barrier height (SBH) is also an important parameter of the MS interface. In principle, the SBH can be determined according to the Schottky-Mott rule as the difference between the metal work function and the conduction-band edge or valenceband edge for n-type or p-type transistors, respectively. [11,12] However, the SBH in an actual device deviates from the Schottky-Mott rule because of the interfacial energy states. [13] This phenomenon is known as Fermi-level pinning (FLP), and the extent

The ORCID identification number(s) for the author(s) of this article can be found under https://doi.org/10.1002/admi.201801528. Black PhosphorusRemoval of excessive heat is one of the key challenges for continuing progress in the high-frequency electronic devices. The shrinking transistor feature size and corresponding increasingly power density are leading to excessive generation of selfheat in high performance integrated circuits and systems. [1,2] This problem is expected to be much more severe in future miniaturized devices and circuits based on low dimensional materials due to alteration in phonon dispersion induced by quantum confinement effects and, enhanced phonon-boundary