Fermi‐Level Pinning Free High‐Performance 2D CMOS Inverter Fabricated with Van Der Waals Bottom Contacts

Abstract

Effective control of 2D transistors polarity is a critical challenge in the process for integrating 2D materials into semiconductor devices. Herein, a doping‐free approach for developing tungsten diselenide (WSe2) logic devices by utilizing the van der Waals (vdWs) bottom electrical contact with platinum and indium as the high and low work function metal respectively is reported. The device structure is free from chemical disorder and crystal defects arising from metal deposition, which enables a near ideal Fermi‐level de‐pinning. With effective controllability of device polarity through metal work function change, a complementary metal‐oxide‐semiconductor field effect transistor inverter with a gain of 198 at a bias voltage of 4.5 V is achieved. This study demonstrates an ultrahigh performance 2D inverter realized by controlling the device polarity from using Fermi‐level pinning‐free vdWs bottom contacts.

Fermi Level Pinning Dependent 2D Semiconductor Devices: Challenges and Prospects

“…Complementary logic functions such as NAND and NOR, high-quality Schottky junction with ideality factor close to 1.0, and sub-1 nm vertical transistors have been demonstrated for dopingfree TMDs using transferred 3D metal contacts. [44,[103][104][105][106] However, the physics behind vanished orbital overlap and interface dipoles for suppressing FLP requires further investigations.…”

Fermi‐Level Pinning‐Free WSe2 Transistors via 2D Van der Waals Metal Contacts and Their Circuits

“…This is similar to that in previously reported multilayered WSe 2 transistors, where direct metallization was employed to form the contacts. [14,20] This observation indicates that the Fermi level is pinned closer to the conduction band edge of WSe 2 , and thus a low electron barrier is formed at the interface between Pd and WSe 2 . Besides, devices fabricated with Au metal also exhibited a similarly controllable polarity (Figure S9, Supporting Information).…”

“…the valence band edge than to the conduction band edge. [19] However, most reported 3D metal-contacted multilayer WSe 2 exhibit n-type characteristics because of strong Fermi-level pinning, [20] as illustrated in the left panel of Figure 1a. Theoretical studies have suggested that the use of vdW 2D metals is an ultra-clean and damage-free approach to solving this pinning issue.…”

Fermi-level pinning-free WSe2 transistors via 2D van der Waals metal contacts and their complementary logic gate circuits

“…This is similar to that in previously reported multilayered WSe2 transistors, where direct metallization was employed to form the contacts. 12,15 This observation indicates that the Fermi level is pinned closer to the conduction band edge of WSe2, and thus a low electron barrier is formed at the interface between Pd and WSe2. For a clear estimation, we tested 20 devices to obtain the statistical variation in carrier polarity (Fig.…”

“…14 However, most reported Pd-contacted multilayer WSe2 and MoS2 FETs exhibit n-type characteristics because of Fermi-level pinning. 15 Theoretical studies have suggested that the use of vdW 2D metals is an effective, doping-free approach to solving this pinning issue. 16,17 Inspired by this, we explore Cl-SnSe2 as a promising 2D metal for hole injection into 2D semiconductors.…”