In this work, we propose an efficient and accurate full-chip thermomechanical stress and reliability analysis tool and design optimization methodology to alleviate mechanical reliability issues in 3D ICs. First, we analyze detailed thermo-mechanical stress induced by TSVs in conjunction with various associated structures such as landing pad and dielectric liner. Then, we explore and validate the use of the linear superposition principle of stress tensors and demonstrate the accuracy of this method against detailed finite element analysis (FEA) simulations. Next, we apply this linear superposition method to full-chip stress simulation and a reliability metric named the von Mises yield criterion. Finally, we propose a design optimization methodology to mitigate the mechanical reliability problems in 3D ICs. Our experimental results demonstrate the effectiveness of our methodology.
Abstract-With the extensive research on through-silicon-via (TSV) and die-stacking technology from both academia and industry, mainstream production of 3D ICs is expected in a near future. However, power delivery is believed to be one of the most challenging problems in 3D ICs. A main objective of the 3D power/ground (P/G) network optimization is to minimize the usage of P/G TSVs while satisfying power supply noise constraint. P/G TSVs consume a considerable amount of routing resources unless designed carefully. In this work, we first investigate the impact of P/G TSVs on the power supply noise as well as 3D IC layouts. We perform sign-off static IR-drop analysis on GDSII layouts of 2D and 3D IC designs using commercial-grade tools. We also explore the impact of 3D P/G network topology on IRdrop by varying P/G TSV pitch. Next, we propose a non-regular P/G TSV placement algorithm to further reduce the number of P/G TSVs used while satisfying the given IR-drop noise requirement. Compared with the conventional regular structure, our non-regular P/G TSV placement algorithm reduces the P/G TSV count, wirelength, and footprint area by 59.3%, 3.4%, and 3.5% on average, respectively.
We describe the design and analysis of 3D-MAPS, a 64-core 3D-stacked memory-on-processor running at 277 MHz with 63 GB/s memory bandwidth, sent for fabrication using Tezzaron's 3D stacking technology. We also describe the design flow used to implement it using industrial 2D tools and custom add-ons to handle 3D specifics.
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