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In this paper, we report on an increase in emission intensity of up to 10 nW/µm2 that has been realized with a new novel two junction, diagonal avalanche control, and minority carrier injection silicon complementary metal–oxide–semiconductor (CMOS) light emitting device (LED). The device utilizes a four-terminal configuration with two embedded shallow n+p junctions in a p substrate. One junction is kept in deep-avalanche and light-emitting mode, while the other junction is forward biased and minority carrier electrons are injected into the avalanching junction. The device has been realized using standard 0.35 µm CMOS design rules and fabrication technology and operates at 9 V in the current range 0.1–3 mA. The optical output power is about one order of magnitude higher for previous single-junction n+p light-emitting devices while the emission intensity is about two orders of magnitude higher than for single-junction devices. The optical output is about three orders of magnitude higher than the low-frequency detectivity limit of silicon p–i–n detectors of comparable dimensions. The realized characteristics may enable diverse optoelectronic applications in standard-CMOS-silicon-technology-based integrated circuitry.

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The structural properties of high porosity nanoporous silicon were researched with the manufacture of integrated nano‐explosive devices in mind. A three‐dimensional nanoporous layer structural model, consisting of cylindrical crystallites, is proposed. Model parameters are derived from gravimetric techniques and the electrochemical etching of high porosity nanoporous silicon layers. A gravimetric experimental technique is described whereby the pore dimensions and specific surface area of nanoporous regions can be determined. An inverse relationship between pore size and specific surface area is found, with a constant specific surface area times pore diameter product. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

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