The inceptions of multilevel inverters (MLI) have caught the attention of researchers for medium and high power applications. However, there has always been a need for a topology with a lower number of device count for higher efficiency and reliability. A new single-phase MLI topology has been proposed in this paper to reduce the number of switches in the circuit and obtain higher voltage level at the output. The basic unit of the proposed topology produces 13 levels at the output with three dc voltage sources and eight switches. Three extentions of the basic unit have been proposed in this paper. A detailed analysis of the proposed topology has been carried out to show the superiority of the proposed converter with respect to the other existing MLI topologies. Power loss analysis has been done using PLECS software, resulting in a maximum efficiency of 98.5%. Nearest level control (NLC) pulse-width modulation technique has been used to produce gate pulses for the switches to achieve better output voltage waveform. The various simulation results have been performed in the PLECS software and a laboratory setup has been used to show the feasibility of the proposed MLI topology.INDEX TERMS DC-AC converter, multilevel inverter, reduce switch count, nearest level control (NLC).

A new triple voltage boosting switched-capacitor multilevel inverter (SCMLI) is presented in this paper. It can produce 13-level output voltage waveform by utilizing 12 switches, three diodes, three capacitors, and one DC source. The capacitor voltages are self-balanced as all the three capacitors present in the circuit are connected across the DC source to charge it to the desired voltage level for several instants in one fundamental cycle. A detailed comparative analysis is carried to show the advantages of the proposed topology in terms of the number of switches, number of capacitors, number of sources, total standing voltage (TSV), and boosting of the converter with the recently published 13-level topologies. The nearest level control (NLC)-based algorithm is used for generating switching signals for the IGBTs present in the circuit. The TSV of the proposed converter is 22. Experimental results are obtained for different loading conditions by using a laboratory hardware prototype to validate the simulation results. The efficiency of the proposed inverter is 97.2% for a 200 watt load.

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As the applications of power electronic converters increase across multiple domains, so do the associated challenges. With multilevel inverters (MLIs) being one of the key technologies used in renewable systems and electrification, their reliability and fault ride-through capabilities are highly desirable. While using a large number of semiconductor components that are the leading cause of failures in power electronics systems, fault tolerance against switch open-circuit faults is necessary, especially in remote applications with substantial maintenance penalties or safety-critical operation. In this paper, a fault-tolerant asymmetric reduced device count multilevel inverter topology producing an 11-level output under healthy conditions and capable of operating after open-circuit fault in any switch is presented. Nearest-level control (NLC) based Pulse width modulation is implemented and is updated post-fault to continue operation at an acceptable power quality. Reliability analysis of the structure is carried out to assess the benefits of fault tolerance. The topology is compared with various fault-tolerant topologies discussed in the recent literature. Moreover, an artificial intelligence (AI)-based fault detection method is proposed as a machine learning classification problem using decision trees. The fault detection method is successful in detecting fault location with low computational requirements and desirable accuracy.

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An 11-level switched-capacitor multilevel inverter (SCMLI) with 2.5 times boosting feature is presented in this paper. It can produce an 11-level output voltage waveform by utilizing 14 switches, 3 capacitors, 2 diodes, and 1 DC source. Only nine driver circuits are needed as the topology has three pairs of complementary switches and two bidirectional switches. It has inherent capacitor self-balancing property as the capacitors are connected across the DC voltage source during several states within a fundamental cycle to charge the capacitors to the input voltage. A detailed comparison shows the effectiveness of the proposed topology in terms of the number of switches, number of capacitors, number of sources, total standing voltage (TSV), efficiency, and boosting ability with the state-of-art recently proposed circuits. Subsequently, the performance of the proposed SCMLI is validated experimentally utilizing the nearest level control (NLC), a fundamental frequency-based switching technique.

In recent times, multilevel inverters (MLIs) have become very popular for commercial and industrial applications. Here, an eleven-level inverter and its power flow control are presented. The presented topology has a lesser component count than other existing topologies, thus reducing the devices and overall cost of the inverter. This inverter comprises six bidirectional switches, two DC sources, one four-quadrant switch, and two capacitors for the voltage divider circuit. The conduction modes and corresponding switching states of the presented eleven-level inverter are shown in detail. Further, the apparent power control of the presented inverter under grid-connected operation is discussed, which provides simultaneous active and reactive power control over the power injected into the grid. Switching and conduction losses are calculated for 3 and 6 kVA grid injected power at 0.8 power factor lagging. The obtained results show that the total harmonic distortion (THD) of the inverter output voltage and grid current is 12.10% and 0.23%, respectively, under 6 kVA power transfer conditions. The real-time analysis is also carried out for 3 and 6 kVA power transfer conditions for the presented eleven-level inverter to validate the active and reactive power flow control.

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