Asymmetric Multilevel Inverter Topology and Its Fault Management Strategy for High-Reliability Applications

Abstract

As the applications of power electronic converters increase across multiple domains, so do the associated challenges. With multilevel inverters (MLIs) being one of the key technologies used in renewable systems and electrification, their reliability and fault ride-through capabilities are highly desirable. While using a large number of semiconductor components that are the leading cause of failures in power electronics systems, fault tolerance against switch open-circuit faults is necessary, especially in remote applications with substantial maintenance penalties or safety-critical operation. In this paper, a fault-tolerant asymmetric reduced device count multilevel inverter topology producing an 11-level output under healthy conditions and capable of operating after open-circuit fault in any switch is presented. Nearest-level control (NLC) based Pulse width modulation is implemented and is updated post-fault to continue operation at an acceptable power quality. Reliability analysis of the structure is carried out to assess the benefits of fault tolerance. The topology is compared with various fault-tolerant topologies discussed in the recent literature. Moreover, an artificial intelligence (AI)-based fault detection method is proposed as a machine learning classification problem using decision trees. The fault detection method is successful in detecting fault location with low computational requirements and desirable accuracy.

A novel voltage boosting switched‐capacitor 19‐level inverter with reduced component count

“…Firstly, it is done on the basis of fault-tolerant operation of the circuit. These studies are done in literature, [26][27][28][29][30] where in case of fault an auxiliary path is used to cover the switch fault. Secondly, the mean time interval to failure (MTTF) of the circuit is estimated; if it is high, the reliability of the circuit is high.…”

A Single Source Switched-Capacitor 13-Level Inverter with Triple Voltage Boosting and Reduced Component Count

“…The conduction loss in an IGBT is caused due to load current flowing through it, which is expressed as, P cond_sw = V on_sw × I on sw + R on sw × I 2 rms_sw (12) where V on_sw and R on_sw are the forward voltage drop and on-state resistance of the switch. I av_sw and I rms_sw are the respective average and RMS values of switch current.…”

“…In [10] the number of switches is the same as [9] with a reduced number of sources, but the number of capacitors used has increased to four. References [12,14,15] produce higher gain but require more switches as compared to the proposed inverter. Moreover, the TSV of these topologies are higher than the proposed topology.…”

“…To overcome these issues, researchers have proposed a self-balanced switched-capacitor multilevel inverter (SCMLI), which can synthesize the desired voltage levels at the output using fewer components and reduced control complexity [6][7][8][9][10][11][12]. Several SCMLIs has been presented by researchers utilizing fewer components to realize the desired multilevel output voltage.…”

“…To reduce the number of switches, the authors in [19] used 19 switches for generating voltage boosting of six, but the TSV of the inverter circuit increased to 39. A detailed review on the recently published multilevel inverter topologies to find the most suitable applications with reduced device count is published in [7][8][9][10][11][12]. In the case of lower solar PV voltages, a high gain DC-DC converter along with multilevel inverter can be used to boost the PV voltage for obtaining desired output voltage for grid integration [24][25][26].…”