The energy distribution of ballistic electrons in a dc/rf hybrid parallel-plate capacitively coupled plasma reactor was measured. Ballistic electrons originated as secondaries produced by ion and electron bombardment of the electrodes. The energy distribution of ballistic electrons peaked at the value of the negative bias applied to the dc electrode. As that bias became more negative, the ballistic electron current on the rf substrate electrode increased dramatically. The ion current on the dc electrode also increased.

Measurements of electron temperatures ͑T e ͒ and electron energy distribution functions ͑EEDFs͒ in a dual frequency capacitively coupled etcher were performed by using trace rare gas optical emission spectroscopy ͑TRG-OES͒. The parallel plate etcher was powered by a high frequency ͑60 MHz͒ "source" top electrode and a low frequency ͑13.56 MHz͒ "substrate" bottom electrode. T e first increased with pressure up to ϳ20 mTorr and then decreased at higher pressures. Increasing the bottom rf power resulted in higher electron temperatures. Electron temperatures in 90% CF 4 +10% O 2 plasmas were similar to those in 80% CF 4 +20% O 2 plasmas. EEDF exhibited bi-Maxwellian characteristics with enhanced high energy tail, especially at pressures Ͼ20 mTorr.

As feature geometries decrease, the budgeted error for process variations decreases as well. Keeping these variations within budget is especially important in the area of gate linewidth control. Because of this, wafer-to-wafer control of gate linewidth becomes increasingly necessary. This paper shows results from 300 mm wafers with 90 nm technology that were trimmed during the gate formation process on an etch platform. After the process that opened the gate hard mask and stripped the resist, the wafers were measured using both an integrated scatterometer and a stand-alone CD-SEM. The measurements were then used to determine the appropriate amount to be trimmed by the Chemical Oxide Removal (COR) chamber that is also integrated onto the etch system. After the wafers were trimmed and etched, they were again measured on the integrated scatterometer and stand-alone CD-SEM. With the CD-SEM as the Reference Measurement System (RMS), Total Measurement Uncertainty (TMU) analysis was used to optimize the Optical Digital Profilometry (ODP) model, thus facilitating a significant reduction in gate linewidth variation. Because the measurement uncertainty of the scatterometer was reduced to a level approaching or below that of the RMS, an improvement to TMU analysis was developed. This improvement quantifies methods for determining the measurement uncertainty of the RMS under a variety of situations.

The end-boundary floating-surface sheath potential, electron and ion energy distribution functions (EEDf , IEDf ) in the low-pressure non-ambipolar electron plasma (NEP) are investigated. The NEP is heated by an electron beam extracted from an inductively coupled electron-source plasma (ICP) through a dielectric injector by an accelerator located inside the NEP. This plasma's EEDf has a Maxwellian bulk followed by a broad energy continuum connecting to the most energetic group with energies around the beam energy. The NEP pressure is 1-3 mTorr of N 2 and the ICP pressure is 5-15 mTorr of Ar. The accelerator is biased positively from 80 to 600 V and the ICP power range is 200-300 W. The NEP EEDf and IEDf are determined using a retarding field energy analyser. The EEDf and IEDf are measured at various NEP pressures, ICP pressures and powers as a function of accelerator voltage. The accelerator current and sheath potential are also measured. The IEDf reveals mono-energetic ions with adjustable energy and it is proportionally controlled by the sheath potential. The NEP end-boundary floating surface is bombarded by a mono-energetic, space-charge-neutral plasma beam. When the injected energetic electron beam is adequately damped by the NEP, the sheath potential is linearly controlled at almost a 1 : 1 ratio by the accelerator voltage. If the NEP parameters cannot damp the electron beam sufficiently, leaving an excess amount of electron-beam power deposited on the floating surface, the sheath potential will collapse and become unresponsive to the accelerator voltage.

Gate patterning is critical to the final yield and performance of logic devices. Because of this, gate linewidth control is viewed by many as the most critical application for integrated metrology on etch systems. For several years, integrated metrology and wafer-level process control have been used in high volume manufacturing of 90 and 65nm polysilicon gate etch [1], [3], [17], [22]. These wafer-level CD control systems have shown the ability to significantly reduce CD variation. With gate linewidth under control (< 2nm 3σ wafer-to-wafer), the next parameter to impact gate electrical performance is side wall angle (SWA). SWA had not been considered a critical control parameter due to the difficulty of measurement with conventional scanning electron microscope (SEM). With scatterometry, SWA measurement of litho and etch profiles are included with the critical dimension (CD) measurements. Recently, it has become visible that the polysilicon SWA correlates to electrical device parameters, and is thus, an important parameter to control. This paper will examine the current relationship between litho and etch profile control, determine potential limitations for future technology nodes, and introduce novel etch process control techniques based on multiple input multiple output (MIMO) modeling.