A novel ultra-low phase noise and high power integrated oscillator is presented in this letter. The proposed oscillator, based on GaN-on-SiC high electron mobility transistor (HEMT) with 0.25 µm gate length and 800 µm gate width, delivers 21 dBm output power when biased at V GS = -3 V and V DD = 28 V. Phase noise was measured to be -112 dBc/Hz at 100 kHz offset and -135 dBc/Hz at 1 MHz offset from 7.9 GHz carrier, respectively. To the best of our knowledge, it achieves the lowest phase noise compared to other GaN HEMT based integrated oscillators. It is also comparable in performance to the state-of-the-art ultra-low phase noise oscillators designed in InGaP technology, while delivering more than 10 times higher output power. In addition, this oscillator also exhibits a minimum second harmonic suppression of 28.65 dBc and more than 60 dBc third harmonic suppression. The chip size is 1.1 × 0.6 mm 2 . The results show that the proposed oscillator has the potential to be used for both low phase noise and high power microwave source applications.
This letter presents a fully integrated Class-J GaN MMIC power amplifier (PA), which is fabricated in Woolfspeed 0.25 um GaN-on-SiC technology. This PA is the first published design for the emerging IEEE 802.11ax application in literature. When tested with 80MHz 256-QAM 802.11ax signal with 11.25 dB peak-to-average power ratio (PAPR), the PA delivers average output power of 27.3 to 30.3 dBm from 4.9 to 5.9 GHz, with power-added efficiency (PAE) of 16.7% to 27.3%, while meeting the standard specification of error vector magnitude (EVM) below -32 dB.
WiFi cannot effectively handle the demands of device-to-device communication between phones, due to insufficient range and poor reliability. We make the case for using IEEE 802.11p DSRC instead, which has been adopted for vehicle-to-vehicle communications, providing lower latency and longer range. We demonstrate a prototype motivated by a novel fabrication process that deposits both III-V and CMOS devices on the same die. In our system prototype, the designed RF front-end is interfaced with a baseband processor on an FPGA, connected to Android phones. It consumes 0.02uJ/bit across 100m assuming free space. Application-level power control dramatically reduces power consumption by 47-56%.
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