This paper presents the design guidelines of the synthetic quasi-TEM transmission line (TL) based on standard 0.18-m one-poly six-metal complementary metal-oxide-semiconductor (CMOS) technology. The synthetic quasi-TEM TL, also called the complementary-conducting-strip transmission line (CCS TL), is composed of five structural parameters to synthesize its guiding characteristics. Twenty-four designs of CCS TL are reported, with the following unique attributes. First, a characteristic impedance range of 8.62-104.0 is yielded. Second, the maximum value of the slow-wave factor is 4.79, representing an increase of 139.5% over the theoretical limit of the quasi-TEM TL. Third, the ratio of the area of the CCS TL to its corresponding quality factor ( factor) can help to estimate the cost of the loss for the circuit miniaturizations. Additionally, the important CMOS manufacturing of metal density is for the first time involved in the reported TL designs. By following the proposed design methodologies, a practical design example of a -band CMOS rat-race hybrid is reported and experimentally examined in detail to reveal the feasibility of the proposed design guidelines to synthesize the CMOS CCS TL. The chip size without contact pads is 420.0 m 540.0 m. The measured loss and isolation of the hybrid at 36.3 GHz are 3.84 and 58.0 dB, respectively.
Indium tin oxide (ITO) ceramics are bonded with ITO and Cu at 250 °C in air using an active solder Sn3.5Ag4Ti(Ce, Ga). The mechanism for such low temperature soldering of ITO ceramics in air has been investigated. Electron probe microanalyzer (EPMA) analyses reveal that the element oxygen distributes uniformly within the solder matrix after soldering, while Ti segregates effectively at the ITO/solder and Cu/solder interfaces at such a low temperature, giving satisfactory joining results of Cu/Cu, ITO/ITO, and ITO/Cu in air.
This work presents a Ka-band two-way 3 dB Wilkinson power divider using synthetic quasi-transverse electromagnetic (TEM) transmission lines (TLs). The synthetic quasi-TEM TL, also called complementary-conducting-strip TL (CCS TL), is theoretically analyzed. The equivalent TL model, whose production is based on the extracted results, is applied to the power divider design. The prototype is fabricated by the standard 0.18 m 1P6M CMOS technology, showing the circuit size of 210.0 m 390.0 m without contact pads. The measurement results, which match the 50 system, reveal perfect agreements with those of the simulations. The comparison reveals the following characteristics. The divider exhibits an equal power-split with the insertion losses ( 21 and 31 ) of 3.65 dB. The return losses ( 11 22 and 33 ) of the prototype are higher than 10.0 dB from 30.0 to 40.0 GHz.
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