Design of Synthetic Quasi-TEM Transmission Line for CMOS Compact Integrated Circuit

Abstract

This paper presents the design guidelines of the synthetic quasi-TEM transmission line (TL) based on standard 0.18-m one-poly six-metal complementary metal-oxide-semiconductor (CMOS) technology. The synthetic quasi-TEM TL, also called the complementary-conducting-strip transmission line (CCS TL), is composed of five structural parameters to synthesize its guiding characteristics. Twenty-four designs of CCS TL are reported, with the following unique attributes. First, a characteristic impedance range of 8.62-104.0 is yielded. Second, the maximum value of the slow-wave factor is 4.79, representing an increase of 139.5% over the theoretical limit of the quasi-TEM TL. Third, the ratio of the area of the CCS TL to its corresponding quality factor ( factor) can help to estimate the cost of the loss for the circuit miniaturizations. Additionally, the important CMOS manufacturing of metal density is for the first time involved in the reported TL designs. By following the proposed design methodologies, a practical design example of a -band CMOS rat-race hybrid is reported and experimentally examined in detail to reveal the feasibility of the proposed design guidelines to synthesize the CMOS CCS TL. The chip size without contact pads is 420.0 m 540.0 m. The measured loss and isolation of the hybrid at 36.3 GHz are 3.84 and 58.0 dB, respectively.

K-band 100.8 mW beamforming SOC with 249.8 ± 22.8 pico-second group-delay in 0.13 µm CMOS

“…2 shows the first kind of the on-chip transmission line, so-called the multiple complementary-conducting-strip transmission line (MCCS-TL). The conventional single CCS-TL had been extensively demonstrated with its great advantages on the guiding characteristics syntheses [12], more than 50% transmission-line component miniaturization [9], and the superior isolation to integrate the components in RF SOCs [13]. The concept of the MCCS-TL was firstly reported in [14] to realize the 1.57 GHz half-wavelength resonator and K-band power divider in 0.18 µm CMOS 1P6M process [15].…”

“…This paper, to modify the MCCS-TL in CMOS 0.13 µm 1P8M process, combines both meandering and spiraling signal trace to construct the quarter-wavelength CCS-TLs in the power combiner. By following the numerical procedures in [12] with the structural and material parameters in Fig. 2(a), Fig.…”

0-dB insertion loss miniaturized third-order 2.54GHz CMOS active bandpass filter

“…CCS-TL provides flexible syntheses on guiding characteristics for the miniaturization on microwave integrated circuits [11] [12]. Previous works demonstrate that the single trace of CCS-TL is supported in a unit cell [9].…”

Integrating Passive Components With Active Circuits Using Standard Silicon Process for Millimeter-Wave Applications

“…On account of the low loss property of the phase inverter and equal path loss, this rat-race coupler maintains output signals balanced regardless of the substrate loss. Most couplers are created on the silicon substrate with substrate shielding [22][23]. Due to a low effective dielectric constant, the coupler size is large.…”