GPS (Global Positioning System) has become an integral part of a vehicle system which provides speed, time, direction etc besides the navigation data. Speed is one of the primary attributes of vehicle accident. Many lives could have been saved if emergency service could receive accident information timely. This paper proposes to detect an accident from the map matched position of a vehicle by utilizing the GPS speed data and map matching algorithm and send accident location to an Alert Service Center. The GPS provides speed and position in every 0.1 second. The position data will be used in the map matching algorithm to locate the vehicle on the road. The present speed will be compared with the previous speed in every 0.1 second through a Microcontroller Unit. Whenever the speed will be falling below the safe calculated threshold speed, the system will generate an accident situation. It will check the vehicle location from map matching module and generate an accident situation if the vehicle is found outside the road network. This will reduce the false accident detection drastically. The map matched accident location is then sent by utilizing the GSM network. The proposed system will save many accident victims with timely rescue.

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Radio frequency identification (RFID) is the utilization of the radio frequency for the purpose of identification. RFID is lagging behind due to vendor specific solutions and excessive implementation cost. A Wireless Fidelity (WiFi) compatible IEEE 802.11 RFID tag can overcome these limitations. IEEE 802.11 utilizes Direct Sequence Spread Spectrum (DSSS) technique and a matched filter is a vital block in a DSSS system. A low-power and low-area novel adder-less Barker matched filter is proposed in this paper by eliminating the conventional multiple multiplications. The matched filter designed in 0.18 mm CMOS technology achieves average and maximum power consumption of 33.747 mW and 8.08 mW, respectively and chip area of 0.41184 mm 2 only. The simulation result shows the correct matching of data against the threshold value. Compared with the conventional matched filter, the design achieves 25% power reduction (maximum power) and 51% chip area reduction. Therefore, the design will help to implement a low-power matched filter for IEEE 801.11 compatible RFID tag.

Radio frequency identification (RFID) is lagging behind because of vendor specific solutions and expensiveimplementation cost. In particular, the reader is the most expensive part. A WiFi compatible tag was proposed to usethe WNIC as an RFID reader. However, no specific modulator or demodulator was suggested. This paper analyzesthe various IEEE 802.11 standards and their modulation and coding techniques keeping the desired properties of anRFID system in consideration. After the analysis, a digital modulator and demodulator for RFID tag in IEEE 802.11protocol employing Direct Sequence Spread-Spectrum (DSSS) and coding is proposed. A MOD-11 synchronouscounter is designed for the 11-bit encoder which generates the desired Barker code. Data are multiplied with thisBarker code to modulate the data, and the received data are multiplied with the Barker code to demodulate them. Theproposed modulator and demodulator are implemented in 0.18μm CMOS technology. The simulation results showthat 1 bit is spread to 11 bits by the modulator and 11-bit received data are demodulated to 1 bit correctly. Theproposed design is simple, resistant to multipath fading and interference and offers the highest distance with thelowest BER for an RFID tag.

Problem statement: Real-time secure image and video communication is challenging due to the processing time and computational requirement for encryption and decryption. In order to cope with these concerns, innovative image compression and encryption techniques are required. Approach: In this research, we have introduced partial encryption technique on compressed images and implemented the algorithm on Altera FLEX10K FPGA device that allows for efficient hardware implementation. The compression algorithm decomposes images into several different parts. We have used a secured encryption algorithm to encrypt only the crucial parts, which are considerably smaller than the original image, which result in significant reduction in processing time and computational requirement for encryption and decryption. The breadth-first traversal linear lossless quadtree decomposition method is used for the partial compression and RSA is used for the encryption. Results: Functional simulations were commenced to verify the functionality of the individual modules and the system on four different images. We have validated the advantage of the proposed approach through comparison, verification and analysis. The design has utilized 2928 units of LC with a system frequency of 13.42MHz. Conclusion: In this research, the FPGA prototyping of a partial encryption of compressed images using lossless quadtree compression and RSA encryption has been successfully implemented with minimum logic cells. It is found that the compression process is faster than the decompression process in linear quadtree approach. Moreover, the RSA simulations show that the encryption process is faster than the decryption process for all four images tested