Radio frequency identification (RFID) is lagging behind because of vendor specific solutions and expensiveimplementation cost. In particular, the reader is the most expensive part. A WiFi compatible tag was proposed to usethe WNIC as an RFID reader. However, no specific modulator or demodulator was suggested. This paper analyzesthe various IEEE 802.11 standards and their modulation and coding techniques keeping the desired properties of anRFID system in consideration. After the analysis, a digital modulator and demodulator for RFID tag in IEEE 802.11protocol employing Direct Sequence Spread-Spectrum (DSSS) and coding is proposed. A MOD-11 synchronouscounter is designed for the 11-bit encoder which generates the desired Barker code. Data are multiplied with thisBarker code to modulate the data, and the received data are multiplied with the Barker code to demodulate them. Theproposed modulator and demodulator are implemented in 0.18μm CMOS technology. The simulation results showthat 1 bit is spread to 11 bits by the modulator and 11-bit received data are demodulated to 1 bit correctly. Theproposed design is simple, resistant to multipath fading and interference and offers the highest distance with thelowest BER for an RFID tag.
-eural Network (NN) is designed to detect QRS complex from ECG signal. QRS complex detection is essential so that RR-interval can be measured for disease classification and can also be monitoring the heart rate. In this paper, a supervised Neural Network based algorithm has been used to detect R in QRS complex. It was tried to find out the R-peak in QRS complex with missing peak and false peak as well, so that the correct decision can be made by the physician and clinician. The accuracy of finding the R-peak by using the Neural Network was 99.09% averagely and the average percentage of missing and false peak was 00.09%. The technique appears to be exceedingly robust, correctly detects R-peaks even aberrant QRS complexes in noise-corrupted ECGs.
A low power 6-bit CMOS ring based digitally controlled oscillator (DCO) design is presented. The design is proposed based on binary-to-thermometer (BT) decoder current mirror digital-to-analog converter (DAC) and ring-based voltage controlled oscillator (VCO). The DCO is implemented using 0.18 µm CEDEC Mentor Graphic CMOS process at 2.0 V supply voltage. The simulation results show that the proposed DCO consumed only 9.5764 mW of power besides the output voltage is 1.8121 V and local oscillator clock frequency is 33 MHz. The phase noise parameter is-132 dBc/Hz with an offset frequency of 100 kHz has also been reported for the proposed circuits.
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