No abstract

The large bandwidth of the 60 GHz frequency band enables wireless short-range applications with data rates of several Gbit/s. The German project EASY-A has focused on early prototype implementations for selected applications, although no generally accepted 60 GHz standard has been available at the time. The implementations are based on application-oriented physical layer designs and link-budget investigations that account for the scenario-specific channel characteristics and for different integration technologies. This paper discusses the results of these investigations and details the hardware implementation of the digital baseband processing that relies on considerable parallelization. The link-budget results show that SiGe technology allows for 1 Gbit/s at a range of 3.5 m in non-line-of-sight environments, while up to 10 Gbit/s are feasible at more than 1 m in case of strong line of sight.

No abstract

No abstract

No abstract

A novel request-driven globally asynchronous locally synchronous (GALS) technique for the system integration of complex digital blocks is proposed. For this new GALS technique, an asynchronous wrapper compliant is developed and evaluated. This proposed GALS technique is applied to a baseband processor compatible with the wireless LAN standard IEEE 802.11a. The developed GALS baseband processor chip is fabricated and measured. Besides improvements of the system integration process, a 5 dB reduction in electromagnetic interference, 30% reduction in instantaneous supply current variation, and similar dynamic power consumption as in the synchronous baseband processor is achieved.

We devise a low-complexity synchronization and channel estimation scheme intended for future 60 GHz wireless personal area networks (WPANs). We show through simulation that a good frame detection rate and good synchronization performance is achieved even for relatively high phase noise.

This paper presents a 5 GHz wideband I/Q modulator/demodulator for 650 MHz OFDM signal bandwidth, which is integrated with a 5 GHz phase locked loop for I/Q generation. The quadrature signals are derived from a 10 GHz CMOS VCO followed by a bipolar frequency divider. The phase noise at 1 MHz offset is −112 dBc/Hz for the modulator as well as for the demodulator. The chips were produced in a 0.25 μm SiGe BiCMOS technology. The signal-to-noise ratio (SNR) of transmitted/received OFDM signal and the corresponding I/Q mismatch versus baseband frequency are given. The modulator achieves an SNR of 22–23 dB, and the demodulator realizes an SNR up to 22 dB. The modulator reaches a data rate of 2.16 Gbit/s using 64 QAM OFDM, and the demodulator realizes 1.92 Gbits/s.