Performance and complexity analysis of channel coding schemes for multi-Gbps wireless communications

Marinkovic, Miroslav; Krstić, Miloš; Grass, Eckhard; Piz, Maxim

doi:10.1109/pimrc.2012.6362670

Cited by 5 publications

(4 citation statements)

References 10 publications

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“…It should be noted that energy is dependent upon the number of Galois field multiplications (8) and additions (9), which in the case of RS(255, k) decoding, are asymptotically (n 2 ) and can be determined for our implementation [38] as follows: 1V. Surprisingly, the clock speed of our design scales almost linearly with the voltage (Fig.…”

Section: A Energy Consumptionmentioning

confidence: 89%

“…The ARQ requires bidirectional communication, even if the user data flow is unidirectional, and therefore the data link layer transmitter has similar complexity as the receiver. Both units own a parallel array of eight RS encoders and decoders [38] with aggregated processing speed equivalent to 16 × 10.313 = 165 Gbps. All other processing is fast enough to handle the 165 Gbps data rate in a single thread.…”

Section: F Link Adaptationmentioning

confidence: 99%

“…1. The dual port static RAM memories (FIFOs) needed for RS implementation [38] are replaced by Flip-Flop (FF) arrays. This solution sounds insane from the power and area point of view, but the memories are the main bottleneck of throughput in our design.…”

Section: Asic Synthesis and Layoutmentioning

confidence: 99%

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Data Link Layer Processor for 100 Gbps Terahertz Wireless Communications in 28 nm CMOS Technology

et al. 2019

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In this paper, we show our 165 Gbps data link layer processor for wireless communication in the terahertz band. The design utilizes interleaved Reed-Solomon codes with dedicated link adaptation, fragmentation, aggregation, and hybrid-automatic-repeat-request. The main advantage is the low-chip area required to fabricate the processor, which is at least two times lower than the area of low-density paritycheck decoders. Surprisingly, our solution loses only ∼1 dB gain when compared to high-speed low-density parity-check decoders. Moreover, with only 2.38 pJ/bit of energy consumption at 0.8 V, one of the best results in the class of comparable implementations has been achieved. Alongside, we show our vision of a complete 100 Gbps wireless transceiver, including radio frequency frontend and baseband processing. For the baseband realization, we propose a parallel sequence spread spectrum and channel combining at the baseband level. Challenges to high-speed wireless transmission at the terahertz band are addressed as well. To the authors' best knowledge, it is one of the first data link layer implementations that deal with a data rate of ≥ 100 Gbps. INDEX TERMS 100 Gbps wireless, terahertz communication, Reed-Solomon coding, data link layer. The associate editor coordinating the review of this manuscript and approving it for publication was Khursheed Aurangzeb. FIGURE 1. Discussed wireless radio-transceiver system. and baseband implementations. Fig. 1 depicts the architecture of the discussed wireless radio-transceiver. A. CHALLENGES TO HIGH-SPEED WIRELESS COMMUNICATIONS Ultra-high speed wireless systems require either very high bandwidth or very high bandwidth efficiency. In cellular architectures like LTE or 5G high bandwidth efficiency is in the focus. This is due to the limited bandwidth in the available radio bands. Increasing the bandwidth efficiency requires a corresponding increase in signal processing power

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Section: A Energy Consumptionmentioning

confidence: 89%

Section: F Link Adaptationmentioning

confidence: 99%

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Data Link Layer Processor for 100 Gbps Terahertz Wireless Communications in 28 nm CMOS Technology

et al. 2019

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“…That is the easiest approach to deal with the problem. The second solution is to redesign the implemented RS entity, that it can natively support the RS(255, 223) [21]. The both approaches are compared in terms of consumed logic area (Fig.…”

Section: Performance Of the Fpga Implementationmentioning

confidence: 99%

100 Gb/s Data Link Layer - from a Simulation to FPGA Implementation

Łopaciński,

Brzozowski,

Kraemer

et al. 2016

JTIT

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In this paper, a simulation and hardware implementation of a data link layer for 100 Gb/s terahertz wireless communications is presented. In this solution the overhead of protocols and coding should be reduced to a minimum. This is especially important for high-speed networks, where a small degradation of efficiency will lower the user data throughput by several gigabytes per second. The following aspects are explained: an acknowledge frame compression, the optimal frame segmentation and aggregation, Reed-Solomon forward error correction, an algorithm to control the transmitted data redundancy (link adaptation), and FPGA implementation of a demonstrator. The most important conclusion is that changing the segment size influences the uncoded transmissions mostly, and the FPGA memory footprint can be significantly reduced when the hybrid automatic repeat request type II is replaced by the type I with a link adaptation. Additionally, an algorithm for controlling the Reed-Solomon redundancy is presented. Hardware implementation is demonstrated, and the device achieves net data rate of 97 Gb/s.

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Improving energy efficiency using a link adaptation algorithm dedicated for 100 Gbps wireless communication

Lopacinski

Brzozowski

Kraemer

et al. 2017

AEU - International Journal of Electronics and Communications

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Performance and complexity analysis of channel coding schemes for multi-Gbps wireless communications

Cited by 5 publications

References 10 publications

Data Link Layer Processor for 100 Gbps Terahertz Wireless Communications in 28 nm CMOS Technology

Data Link Layer Processor for 100 Gbps Terahertz Wireless Communications in 28 nm CMOS Technology

100 Gb/s Data Link Layer - from a Simulation to FPGA Implementation

Improving energy efficiency using a link adaptation algorithm dedicated for 100 Gbps wireless communication

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