System integration by request-driven GALS design

Abstract

A novel request-driven globally asynchronous locally synchronous (GALS) technique for the system integration of complex digital blocks is proposed. For this new GALS technique, an asynchronous wrapper compliant is developed and evaluated. This proposed GALS technique is applied to a baseband processor compatible with the wireless LAN standard IEEE 802.11a. The developed GALS baseband processor chip is fabricated and measured. Besides improvements of the system integration process, a 5 dB reduction in electromagnetic interference, 30% reduction in instantaneous supply current variation, and similar dynamic power consumption as in the synchronous baseband processor is achieved.

Developing mesochronous synchronizers to enable 3D NoCs

“…GALS systems [13,14,16] attach together a number of synchronous building blocks, and provide asynchronous facilities for the inter-block communication. While some of the tool maturity issues mentioned above still hold, the encapsulation of mixed-clock concerns within well-defined boundaries, which can be validated separately, provides a more conservative, and possibly more promising, solution to the interconnection issue.…”

“…While some of the tool maturity issues mentioned above still hold, the encapsulation of mixed-clock concerns within well-defined boundaries, which can be validated separately, provides a more conservative, and possibly more promising, solution to the interconnection issue. Several ways to synchronize clock domains at the boundaries exist, such as interleaving pipeline registers, using dual-clock FIFOs, adding programmable delays [17], deploying synchronous-to-asynchronous wrappers [13]. Although some of these solutions (for instance, dual-clock FIFOs) are very flexible, allowing for arbitrary clock frequencies in the sender and receiver domain, they all have one or more drawbacks, ranging from robustness to implementation complexity, from high latency to large area overhead.…”

Design Space Exploration for Networks On-chip

“…Practical GALS implementations may form much more complex structures, such as bus [149] or NoC structures [87], for inter-block communications, and use different data synchronization mechanisms. Additionally, the GALS paradigm does not rely on absolute timing information and therefore favours modularity, by means of local islands of synchronicity that can be arbitrarily combined to build up larger systems [83]. NoC architectures are generally viewed as an ideal target for application of the GALS paradigm [87].…”