2011
DOI: 10.1007/s10836-011-5195-x
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An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology

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Cited by 7 publications
(1 citation statement)
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“…[60] argues that reintroducing clocks in clockless designs defeats the purpose and limits the potential of asynchronous designs. This argument is backed by Cheng and Li's assessment in [61], where they have warned about the possibility of reliability issues and timing violations within an NCL system due to the inclusion of clocked hardware. To overcome these limitations, [60] proposed a completely homogenous design-for-test (DFT) methodology for NCL circuits.…”
Section: Significantlymentioning
confidence: 99%
“…[60] argues that reintroducing clocks in clockless designs defeats the purpose and limits the potential of asynchronous designs. This argument is backed by Cheng and Li's assessment in [61], where they have warned about the possibility of reliability issues and timing violations within an NCL system due to the inclusion of clocked hardware. To overcome these limitations, [60] proposed a completely homogenous design-for-test (DFT) methodology for NCL circuits.…”
Section: Significantlymentioning
confidence: 99%