A piezoelectric FPW-sensor has been developed for a point of care device in this work. The Bio- MEMS FPW-sensor consists of an electrode configuration termed as an interdigital transducer (IDT) placed on a membrane. An input IDT excites and an output IDT detects the propagating acoustic waves through a PZT layer. Design optimizations and fabrication improvements of the FPW-sensor led to significantly reduced attenuation of the wave signal and the damping of the propagating waves between the IDTs. The working principle of mass loading is shown using different low-viscous liquids. A densitydependent sensitivity of -0.39 MHz/g/cm³ was evaluated. After the membrane was functionalized, the Bio-MEMS FPW-sensor was used to measure a specific chemokine in complex solution. By design improvements, the resolution was significantly increased from 0.7 Hz/nM to 14 Hz/nM.
Backside illuminated technologies have been used in complementary metal–oxide–semiconductor image sensors for years and are finding a renewed interest and are being investigated for imagers and detectors in light detection and ranging applications. Coupled with the improved performance facilitated through 3D integration, the thinning of bonded wafers has become a crucial processing step. In this study, an alternate and potentially more cost-effective method has been explored using an HNA (hydrofluoric, nitric, acetic)wet etch for backside thinning of bonded epitaxial P+/P- silicon wafers. By utilizing a dopant concentration gradient, P+ silicon is selectively etched and P- silicon can be effectively used as an etch stop. Several HNA concentrations were explored to determine ratios that yield high P+ silicon etch rates while maintaining high P+/P- selectivity. Furthermore, bath life, spiking scheme, and repeatability were examined using a large wafer sample size with the goal of developing a full process flow.
Backside illuminated (BSI) technologies have been commonly used in CMOS image sensors and are finding a renewed interest for images and detectors for LiDAR application that has been driven by the automotive industry. As the integration of signal processing into microelectronic detectors progresses, active area and fill factor become issues for monolithic solutions. Processing the detector and readout circuitry (ROIC) on different wafers allows for the separate optimization of cost and performance. As a result, backside thinning had become a critical step in the process flow for BSI technologies, with the backside of wafers needed to be thinned down to within microns of active area to effectively couple incident photons. Conventional approaches to backside thinning utilize the buried oxide layer of an SOI wafer, which acts as a reliable etch stop since there are both wet and dry silicon etchants with suitable selectivity to the oxide. Despite the robust method for SOI wafer thinning, there are a few key disadvantages that attract the exploration of alternative routes. For instance, SOI wafers are expensive when compared to conventional epitaxial substrates, with the price reaching up to 5 times more depending on quantities. Additionally, the crystallinity of the silicon film on SOI wafers is typically lower than that of epitaxial silicon, which can lead to a decrease in device performance. Thus, to reduce cost and improve performance, an etch process that uses standard epitaxial substrates provides a favorable alternative. However, a method that can reliably, and precisely thin epitaxial substrates is needed. A possible approach would be to exploit a difference in dopant concentration between the substrate and epitaxial silicon. Doing so would require a wet etchant with sufficient selectivity to etch one of the silicon and use the other as an etch stop. The difficulty with this approach is that a change in dopant concentration is not as chemically distinct as a change in material. As such, reliably achieving precise and uniform final silicon film thicknesses presents a challenge that requires optimization of chemistry. Moreover, for such a method to be implemented on a production scale a working understanding of chemical bath life and wafer to wafer etch repeatability over a large sample size is necessary. This study provides a comprehensive examination on the feasibility and reliability of thinning epitaxial substrates and provides an outline for the development of a wet process that rapidly etches heavily doped substrate silicon (etch rate >5 µm/min) and uses a lightly doped device silicon layer as an etch stop (etch rate <0.2 µm/min). Optimal etchant compositions are investigated to identify a suitable chemistry for the required etch rates and selectivity. Furthermore, the effect of bath life and spiking/regeneration schemes on the performance of the etchant in a in a recirculated chemistry application is then explored. After preliminary development work was completed, the chemistry was used to thin a series of epitaxial wafers to explore the wafer-to-wafer repeatability of the developed process. Acknowledgements This project has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 876659 (iRel40). The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Germany, Austria, Slovakia, Sweden, Finland, Belgium, Italy, Spain, Netherlands, Slovenia, Greece, France, Turkey. Figure 1
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