Current trend is to increase the overall use of electronic systems in daily life. Exemplarily, the complexity of automotive Electronic Control Unit (ECU) systems is rising due to the number of components involved and the tighter interactions between these heterogeneous components (analog, digital hardware or software), resulting in a more and more challenging verification. In this paper, we show that the Universal Verification Methodology (UVM), initially developed for digital systems, can successfully be extended to analog and mixed signal systems. We introduce the UVM-SystemC-AMS framework for functional verification based on SystemC and its AMS extension SystemC-AMS. Using two automotive case studies we demonstrate the flexibility of our approach both for simulation based verification and lab based validation using a Hardware In the Loop (HIL) system.
Each new embedded system tends to integrate more sensors with tight software-driven control, digitally assisted analog circuits, and heterogeneous structure. A more responsive simulation environment is needed to support the co-design and verification of such complex architectures including all its digital hardware/software and analog/multi-physical aspects using Multi-Disciplinary Virtual Prototyping (MDVP). Taking a Micro-Electro-Mechanical System (MEMS) vibration sensor as an example, we introduce a reusable framework based on the state-of-the-art technologies SystemC AMS, Finite Elements/Reduced-Order modeling, and UVM to design, simulate, and verify such systems in their real application context
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