UVM-SystemC-AMS Framework for System-Level Verification and Validation of Automotive Use Cases

Abstract

Current trend is to increase the overall use of electronic systems in daily life. Exemplarily, the complexity of automotive Electronic Control Unit (ECU) systems is rising due to the number of components involved and the tighter interactions between these heterogeneous components (analog, digital hardware or software), resulting in a more and more challenging verification. In this paper, we show that the Universal Verification Methodology (UVM), initially developed for digital systems, can successfully be extended to analog and mixed signal systems. We introduce the UVM-SystemC-AMS framework for functional verification based on SystemC and its AMS extension SystemC-AMS. Using two automotive case studies we demonstrate the flexibility of our approach both for simulation based verification and lab based validation using a Hardware In the Loop (HIL) system.

A novel FPGA-based test-bench framework for SDI stream verification

“…This and other features of UVM facilitate the creating of reusable verification components. During the years, these techniques have been supported by Accellera System Initiative [3] and the advantages of its use are demonstrated in [4] using automotive examples. Verification methods are designed to be general and can be adapted for every testing scenario.…”

Verifying next generation electronic systems

“…Further reading: [48], [49], [50], [51], [52] Learning systems, especially self-adapting and -learning: Driven by the enormous advances in computing power, learning for instance in the form of neural networks, machine learning etc. can now be integrated into these systems.…”