SystemC AMS Extensions: New Language – New Methods – New Applications

Barnasconi, Martin; Damm, Markus; Einwich, Karsten

doi:10.1007/978-3-642-11802-9_4

Cited by 1 publication

(5 citation statements)

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“…SystemC is a C++ library for system-level modeling and simulation of digital systems. An Analog/Mixed-Signal (AMS) extension for the efficient modeling and simulation of analog systems is available as SystemC AMS [4], which can provide simulations that are over 100,000× faster compared to SPICE-level simulations. It supports three Models of Computation (MoC): (1) TDF, (2) Linear Signal Flow (LSF), and (3) Electrical Linear Networks (ELN).…”

Section: Systemc and Systemc Amsmentioning

confidence: 99%

“…The rising complexity of analog circuits and the ever-increasing system integration of analog and digital components have created a bottleneck for analog design verification. A major challenge in this regard is the simulation speed of SPICE-level models [1]. They often fail for large systems due to convergence related problems or are prohibitive in terms of computational time required.…”

Section: Introductionmentioning

confidence: 99%

“…As a consequence, analog designs are moving towards a top-down approach. In this regard, Virtual Prototyping (VP) at the abstraction of Electronic System Level (ESL) is nowadays an established industrial practice [1,[3][4][5][6]. The Timed Data Flow (TDF) Model of Computation (MoC) available in SystemC AMS offers a good trade-off between accuracy and simulation speed at the system level, and can provide a speed increase of over 100,000× [1] in comparison to SPICE-level simulations.…”

Section: Introductionmentioning

confidence: 99%

“…In this regard, Virtual Prototyping (VP) at the abstraction of Electronic System Level (ESL) is nowadays an established industrial practice [1,[3][4][5][6]. The Timed Data Flow (TDF) Model of Computation (MoC) available in SystemC AMS offers a good trade-off between accuracy and simulation speed at the system level, and can provide a speed increase of over 100,000× [1] in comparison to SPICE-level simulations. TDF defines time domain processing, and is used to model the pure algorithmic or procedural description of the underlying design.…”

Section: Introductionmentioning

confidence: 99%

“…A transfer function model captures the frequency response of an analog circuit and provides a suitable platform for applying non-simulation/formal techniques to verify the circuit against its specification. Due to earlier availability and significantly faster simulation speed as opposed to SPICE-level simulations [1], the TDF models provide a design refinement methodology and enable early verification for analog/mixed-signal systems.…”

Section: Introductionmentioning

confidence: 99%

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Equivalence Checking of System-Level and SPICE-Level Models of Linear Circuits

Coşkun

Hassan

Drechsler

2022

Chips

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Due to the increasing complexity of analog circuits and their integration into System-on-Chips (SoC), the analog design and verification industry would greatly benefit from an expansion of system-level methodologies using SystemC AMS. These can provide a speed increase of over 100,000× in comparison to SPICE-level simulations and allow interoperability with digital tools at the system-level. However, a key barrier to the expansion of system-level tools for analog circuits is the lack of confidence in system-level models implemented in SystemC AMS. Functional equivalence of single Laplace Transfer Function (LTF) system-level models to respective SPICE-level models was successfully demonstrated recently. However, this is clearly not sufficient, as the complex systems comprise multiple LTF modules. In this article, we go beyond single LTF models, i.e., we develop a novel graph-based methodology to formally check equivalence between complex system-level and SPICE-level representations of Single-Input Single-Output (SISO) linear analog circuits, such as High-Pass Filters (HPF). To achieve this, first, we introduce a canonical representation in the form of a Signal-Flow Graph (SFG), which is used to functionally map the two representations from separate modeling levels. This canonical representation consists of the input and output nodes and a single edge between them with an LTF as its weight. Second, we create an SFG representation with linear graph modeling for SPICE-level models, whereas for system-level models we extract an SFG from the behavioral description. We then transform the SFG representations into the canonical representation by utilizing three graph manipulation techniques, namely node removal, parallel edge unification, and reflexive edge elimination. This allows us to establish functional equivalence between complex system-level models and SPICE-level models. We demonstrate the applicability of the proposed methodology by successfully applying it to complex circuits.

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Section: Systemc and Systemc Amsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%