As semiconductor device dimensions shrink and packingdensities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of Thin-Film Silicon-On-Insulator (TFSOI) substrates for device fabrication is being explored in order to reduce power consumption and increase performance. SIMOX (Siliconseparation by Implanted Oxygen),' and BESOl ( Bond and Etch back Silicon On Insulator) can be used for device fabrication at this time, however the subject of this study will be CMOS device structures built on SIMOX only. Fabrication of modern MOSFET's requires formation of a silicide in both the poly gate and mono-silicon Source/ Drain regions. In our case the contact silicide under investigation is a TiSi2 layer followed by AI(Cu) metal interconnect lines. TiSi2 has a relatively low contact resistance2 and reduces the series resistance of both source/drain as well as gate regions.The SIMOX starting material consists of a 220 nm active silicon layer separated from the substrate-Si by -400 nm Si02 layer. The active regions of these wafers are subsequently thinned to 100 nm through the use of selective oxidation. Using these thinned wafers as substrates, oxide-isolation, gate-oxidation, polysilicon-gate formation and oxide sidewall formation steps are performed. Arsenic or boron is implanted into the source/drain regions. After high-temperature annealing to activate the dopant, a thin Titanium film (lOnm, 35nm, 45nm, 55nm, or 60nm thick) is deposited over the entire structure. A 650°C Anneal is performed to cause Ti to react with Si in S/D and gate regions. After chemically stripping unreacted Ti, a second anneal is performed to transform the TiSi2 from the higher-resistivity C49 phase2 to the low-resistivity C54 p h a~e .~,~ Electrical measurements of 25 um wide MOS devices were performed and Cross-section TEM (Transmission Electron Microscopy) specimens are fabricated from repeating MOSFET structures 150pm x 2pm in dimension, by conventional dimpling followed by iterative argon ion-milling and TEM investigation.55-60nm Ti deposition on S/D regions resulted in poor electrical contact upon silicidation (see Fig. 3) 10nm Ti resulted once again in poor electrical contact. 35-45nm Ti produced normal electrical results. (see Fig. 4) TEM analysis shows the reason for this electrical behavior. lOnm Ti layers formed TiSi2 layers that were non-uniform (agglomeration and islanding had occurred). 55-60nm Ti layers resulted in a formation of voids at the edges of the silicide. Fig. l a presents an XTEM overview obtained from a structure silicided with 60nm Ti. The S/D and gate regions are indicated on the micro graph. Beneath the polysilicon-gate/ gate-oxide region and above the SIMOX oxide is single-crystal silicon. In the source/drain regions, the SIMOX-silicon has been completely consumed by reaction with Ti. Fig. l b presents a higher-magnification TEM image obtained from the source/gate region of the structure. Between the TiSi2 and the SIMOX-silicon voids are evident that cut across the entire la...
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