Many in-memory computing frameworks demand electronic devices with specific switching characteristics to achieve the desired level of computational complexity. Existing memristive devices cannot be reconfigured to meet the diverse volatile and non-volatile switching requirements, and hence rely on tailored material designs specific to the targeted application, limiting their universality. “Reconfigurable memristors” that combine both ionic diffusive and drift mechanisms could address these limitations, but they remain elusive. Here we present a reconfigurable halide perovskite nanocrystal memristor that achieves on-demand switching between diffusive/volatile and drift/non-volatile modes by controllable electrochemical reactions. Judicious selection of the perovskite nanocrystals and organic capping ligands enable state-of-the-art endurance performances in both modes – volatile (2 × 106 cycles) and non-volatile (5.6 × 103 cycles). We demonstrate the relevance of such proof-of-concept perovskite devices on a benchmark reservoir network with volatile recurrent and non-volatile readout layers based on 19,900 measurements across 25 dynamically-configured devices.

Memristive devices represent a promising technology for building neuromorphic electronic systems. In addition to their compactness and non-volatility features, they are characterized by computationally relevant physical properties, such as state-dependence, non-linear conductance changes, and intrinsic variability in both their switching threshold and conductance values, that make them ideal devices for emulating the bio-physics of real synapses. In this paper we present a spiking neural network architecture that supports the use of memristive devices as synaptic elements, and propose mixed-signal analog-digital interfacing circuits which mitigate the effect of variability in their conductance values and exploit their variability in the switching threshold, for implementing stochastic learning. The effect of device variability is mitigated by using pairs of memristive devices configured in a complementary push-pull mechanism and interfaced to a current-mode normalizer circuit. The stochastic learning mechanism is obtained by mapping the desired change in synaptic weight into a corresponding switching probability that is derived from the intrinsic stochastic behavior of memristive devices. We demonstrate the features of the CMOS circuits and apply the architecture proposed to a standard neural network hand-written digit classification benchmark based on the MNIST data-set. We evaluate the performance of the approach proposed on this benchmark using behavioral-level spiking neural network simulation, showing both the effect of the reduction in conductance variability produced by the current-mode normalizer circuit, and the increase in performance as a function of the number of memristive devices used in each synapse.Neuromorphic computing systems comprise synapse and neuron circuits arranged in a massively parallel manner to support the emulation of large-scale spiking neural networks 1-9 . In many of these systems, and in particular in neuromorphic processing devices designed to overcome the von-Neumann bottleneck problem 7,8,10-14 , the bulk of the silicon real-estate is taken up by synaptic circuits that integrate in the same area both memory and computational primitives. To save area and maximize density in such devices, one possible approach is to implement very basic synapse circuits arranged in dense cross-bar arrays [15][16][17][18][19] . However, such approach is likely to relegate the role of the synapse to a basic multiplier 14,20 . In biology, synapses are extremely sophisticated structures that exhibit complex and powerful computational properties, including temporal dynamics, state-dependence, and stochastic learning behavior. The challenge is to design neuromorphic circuits that emulate these computational properties, and are also compact and low power. Memristive devices have recently emerged as nano-scale devices which provide a promising technology for addressing these problems 31,46 . These devices offer a compact and efficient solution to model synaptic weights since they are non-volatile, have ...

Spiking neural networks (SNNs) employing memristive synapses are capable of life-long online learning. Because of their ability to process and classify large amounts of data in real-time using compact and low-power electronic systems, they promise a substantial technology breakthrough. However, the critical issue that memristor-based SNNs have to face is the fundamental limitation in their memory capacity due to finite resolution of the synaptic elements, which leads to the replacement of old memories with new ones and to a finite memory lifetime. In this study we demonstrate that the nonlinear conductance dynamics of memristive devices can be exploited to improve the memory lifetime of a network. The network is simulated on the basis of a spiking neuron model of mixed-signal digital-analogue sub-threshold neuromorphic CMOS circuits, and on memristive synapse models derived from the experimental nonlinear conductance dynamics of resistive memory devices when stimulated by trains of identical pulses. The network learning circuits implement a spike-based plasticity rule compatible with both spike-timing and rate-based learning rules. In order to get an insight on the memory lifetime of the network, we analyse the learning dynamics in the context of a classical benchmark of neural network learning, that is hand-written digit classification. In the proposed architecture, the memory lifetime and the performance of the network are improved for memristive synapses with nonlinear dynamics with respect to linear synapses with similar resolution. These results demonstrate the importance of following holistic approaches that combine the study of theoretical learning models with the development of neuromorphic CMOS SNNs with memristive devices used to implement life-long on-chip learning.

Spike-based learning with memristive devices in neuromorphic computing architectures typically uses learning circuits that require overlapping pulses from preand post-synaptic nodes. This imposes severe constraints on the length of the pulses transmitted in the network, and on the network's throughput. Furthermore, most of these circuits do not decouple the currents flowing through memristive devices from the one stimulating the target neuron. This can be a problem when using devices with high conductance values, because of the resulting large currents. In this paper we propose a novel circuit that decouples the current produced by the memristive device from the one used to stimulate the post-synaptic neuron, by using a novel differential scheme based on the Gilbert normalizer circuit. We show how this circuit is useful for reducing the effect of variability in the memristive devices, and how it is ideally suited for spike-based learning mechanisms that do not require overlapping pre-and post-synaptic pulses. We demonstrate the features of the proposed synapse circuit with SPICE simulations, and validate its learning properties with high-level behavioral network simulations which use a stochastic gradient descent learning rule in two classification tasks.

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Neural processing systems typically represent data using Leaky Integrate and Fire (LIF) neuron models that generate spikes or pulse trains at a rate proportional to their input amplitudes. This mechanism requires high firing rates when encoding time-varying signals, leading to increased power consumption. Neuromorphic systems that use adaptive LIF neuron models overcome this problem by encoding signals in the relative timing of their output spikes rather than their rate. In this paper, we analyze recent adaptive LIF neuron circuit implementations and highlight the analogies and differences between them and a first-order Σ∆ feedback loop. We propose a new Σ∆ neuron circuit that addresses some of the limitations in existing implementations and present simulation results that quantify the improvements. We show that the new circuit, implemented in a 1.8V , 180nm CMOS process, offers up to 42dB Signal to Distortion Ratio (SDR) and consumes orders of magnitude lower energy. Finally, we also demonstrate how the sigma-delta interpretation enables mapping of real-valued Recurrent Neural Networks (RNNs) to the spiking framework to emphasize the envisioned application of the proposed circuit.

This paper discusses implementations of gradientdescent based learning algorithms on memristive crossbar arrays. The Unregulated Step Descent (USD) is described as a practical algorithm for feed-forward on-line training of large crossbar arrays. It allows fast feed-forward fully parallel on-line hardware based learning, without requiring accurate models of the memristor behaviour and precise control of the programming pulses. The effect of device parameters, training parameters, and device variability on the learning performance of crossbar arrays trained using the USD algorithm has been studied via simulations. Abstract This paper discusses implementations of gradientdescent based learning algorithms on memristive crossbar arrays. The Unregulated Step Descent (USD) is described as a practical algorithm for feed-forward on-line training of large crossbar arrays. It allows fast feed-forward fully parallel on-line hardware based learning, without requiring accurate models of the memristor behaviour and precise control of the programming pulses. The effect of device parameters, training parameters, and device variability on the learning performance of crossbar arrays trained using the USD algorithm has been studied via simulations.There is a significant interest in using memristive devices for computation, in particular in the context of neuromorpic systems [1] and artificial neural networks [2][3][4][5][6][7]. Memristors are typically fabricated in the form of highly-dense crossbar arrays, which naturally lend themselves to the vector-matrix multiplications that are at the core of the neural network algorithms. Memristor-based hardware implementations, while promising low-power high-speed computation, need to address several challenges, such as extreme device variability, complex state-dependent behaviours, or difficulty in integrating active devices within the crossbar. In this paper, we discuss an approximate gradient-descent based learning algorithm, called the Unregulated Step Descent (USD) [8] that addresses these hardware issues, and provides a practical method for training large crossbar arrays in machine learning applications.