Many in-memory computing frameworks demand electronic devices with specific switching characteristics to achieve the desired level of computational complexity. Existing memristive devices cannot be reconfigured to meet the diverse volatile and non-volatile switching requirements, and hence rely on tailored material designs specific to the targeted application, limiting their universality. “Reconfigurable memristors” that combine both ionic diffusive and drift mechanisms could address these limitations, but they remain elusive. Here we present a reconfigurable halide perovskite nanocrystal memristor that achieves on-demand switching between diffusive/volatile and drift/non-volatile modes by controllable electrochemical reactions. Judicious selection of the perovskite nanocrystals and organic capping ligands enable state-of-the-art endurance performances in both modes – volatile (2 × 106 cycles) and non-volatile (5.6 × 103 cycles). We demonstrate the relevance of such proof-of-concept perovskite devices on a benchmark reservoir network with volatile recurrent and non-volatile readout layers based on 19,900 measurements across 25 dynamically-configured devices.
Dedicated hardware implementations of spiking neural networks that combine the advantages of mixed-signal neuromorphic circuits with those of emerging memory technologies have the potential of enabling ultra-low power pervasive sensory processing. To endow these systems with additional flexibility and the ability to learn to solve specific tasks, it is important to develop appropriate on-chip learning mechanisms. Recently, a new class of three-factor spike-based learning rules have been proposed that can solve the temporal credit assignment problem and approximate the error back-propagation algorithm on complex tasks. However, the efficient implementation of these rules on hybrid CMOS/memristive architectures is still an open challenge. Here we present a new neuromorphic building block, called PCM-trace, which exploits the drift behavior of phasechange materials to implement long lasting eligibility traces, a critical ingredient of three-factor learning rules. We demonstrate how the proposed approach improves the area efficiency by > 10× compared to existing solutions and demonstrates a technologically plausible learning algorithm supported by experimental data from device measurements.
Many edge computing and IoT applications require adaptive and on-line learning architectures for fast and low-power processing of locally sensed signals. A promising class of architectures to solve this problem is that of in-memory computing ones, based on event-based hybrid memristive-CMOS devices. In this work, we present an example of such systems that supports always-on on-line learning.To overcome the problems of variability and limited resolution of ReRAM memristive devices used to store synaptic weights, we propose to use only their High Conductive State (HCS) and control their desired conductance by modulating their programming Compliance Current (I CC ). We describe the spike-based learning CMOS circuits that are used to modulate the synaptic weights and demonstrate the relationship between the synaptic weight, the device conductance, and the I CC used to set its weight, with experimental measurements from a 4kb array of HfO 2 -based devices. To validate the approach and the circuits presented, we present circuit simulation results for a standard CMOS 180nm process and system-level behavioral simulations for classifying hand-written digits from the MNIST data-set with classification accuracy of 92.68% on the test set.
Being one-atom thick and tunable simultaneously, graphene plays the revolutionizing role in many areas. The focus of this paper is to investigate the modal characteristics of surface waves in structures with graphene in the far-infrared (far-IR) region. We discuss the effects exerted by substrate permittivity on propagation and localization characteristics of surface-plasmon-polaritons (SPPs) in single-layer graphene and theoretically investigate characteristics of the hybridized surface-phonon-plasmon-polaritons (SPPPs) in graphene/LiF/glass heterostructures. First, it is shown how high permittivity of substrate may improve characteristics of graphene SPPs. Next, the possibility of optimization for surface-phonon-polaritons (SPhPs) in waveguides based on LiF, a polar dielectric with a wide polaritonic gap (Reststrahlen band) and a wide range of permittivity variation, is demonstrated. Combining graphene and LiF in one heterostructure allows to keep the advantages of both, yielding tunable hybridized SPPPs which can be either forwardly or backwardly propagating. Owing to high permittivity of LiF below the gap, an almost 3.2-fold enhancement in the figure of merit (FoM), ratio of normalized propagation length to localization length of the modes, can be obtained for SPPPs at 5–9 THz, as compared with SPPs of graphene on conventional glass substrate. The enhancement is efficiently tunable by varying the chemical potential of graphene. SPPPs with characteristics which strongly differ inside and around the polaritonic gap are found.
, "Plasmonic enhanced terahertz time-domain spectroscopy system for identification of common explosives," Proc. SPIE ABSTRACTIn this study, we present a classification algorithm for terahertz time-domain spectroscopy systems (THz-TDS) that can be trained to identify most commonly used explosives (C4, HMX, RDX, PETN, TNT, composition-B and blackpowder) and some non-explosive samples (lactose, sucrose, PABA). Our procedure can be used in any THz-TDS system that detects either transmission or reflection spectra at room conditions. After preprocessing the signal in low THz regime (0.1 − 3 THz), our algorithm takes advantages of a latent space transformation based on principle component analysis in order to classify explosives with low false alarm rate.
Thinning the active layer's thickness of the semiconductor down to a level comparable with the carriers' diffusion length while keeping its absorption high is an ultimate goal to boost the performance of optoelectronic devices. Strong interference in multilayer structures is one of the promising and practical solutions owing to their simple and large-scale compatible fabrication route. These nanocavity designs not only provide near unity absorption, but they can also be designed in a way that a spectrally selective absorption response can be achieved. In this letter, we will demonstrate the functionality of a metalinsulator-semiconductor (MIS) cavity to obtain spectrally selective ultrathin photodetectors. To prove our theoretical and numerical findings, a 4-nm-thick amorphous silicon (a-Si)-based MIS cavity is designed, fabricated, and characterized. The experimental results show that the optimized cavity design can act as an efficient visible blind ultraviolet (UV) photodetector. The proposed design shows the responsivity values of 120 and 2.5 mA/W in the UV (λ = 350 nm) and visible (λ = 500 nm) regions, respectively.
Dedicated hardware implementations of spiking neural networks that combine the advantages of mixed-signal neuromorphic circuits with those of emerging memory technologies have the potential of enabling ultra-low power pervasive sensory processing. To endow these systems with additional flexibility and the ability to learn to solve specific tasks, it is important to develop appropriate on-chip learning mechanisms. Recently, a new class of three-factor spike-based learning rules have been proposed that can solve the temporal credit assignment problem and approximate the error back-propagation algorithm on complex tasks. However, the efficient implementation of these rules on hybrid CMOS/memristive architectures is still an open challenge. Here we present a new neuromorphic building block, called PCM-trace, which exploits the drift behavior of phasechange materials to implement long lasting eligibility traces, a critical ingredient of three-factor learning rules. We demonstrate how the proposed approach improves the area efficiency by > 10× compared to existing solutions and demonstrates a technologically plausible learning algorithm supported by experimental data from device measurements.
The connectivity in the brain is locally dense and globally sparse - giving rise to a small-world graph. This is a principle that has persisted during the evolution of many species - indicating a universal solution to the efficient routing of information. However, existing circuit architectures for artificial neural networks neither leverage this organization nor do they efficiently support small-world neural network models. Here, we propose the neuromorphic Mosaic: a non-von Neumann systolic architecture that uses distributed memristors, not only for in-memory computing, but also for in-memory routing, to efficiently implement small-world graph topologies. We design, fabricate, and experimentally demonstrate the building blocks of this architecture, using integrated memristors with 130 nm CMOS technology. We demonstrate that neural networks implemented following this approach can achieve competitive accuracy figures compared to equivalent unconstrained and full-precision networks, for three real-time benchmarks: classification of electrocardiography signals, keyword spotting and motor control via reinforcement learning. The Mosaic shows improvements between one and four orders of magnitude, compared to other event-based neuromorphic architectures for routing events across the network. The Mosaic opens up a new scalable approach for designing edge AI systems based on distributed computing and in-memory routing, offering a natural platform onto which architectures inspired by biological nervous systems can be readily mapped.
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