A differential memristive synapse circuit for on-line learning in neuromorphic computing systems

Abstract

Spike-based learning with memristive devices in neuromorphic computing architectures typically uses learning circuits that require overlapping pulses from preand post-synaptic nodes. This imposes severe constraints on the length of the pulses transmitted in the network, and on the network's throughput. Furthermore, most of these circuits do not decouple the currents flowing through memristive devices from the one stimulating the target neuron. This can be a problem when using devices with high conductance values, because of the resulting large currents. In this paper we propose a novel circuit that decouples the current produced by the memristive device from the one used to stimulate the post-synaptic neuron, by using a novel differential scheme based on the Gilbert normalizer circuit. We show how this circuit is useful for reducing the effect of variability in the memristive devices, and how it is ideally suited for spike-based learning mechanisms that do not require overlapping pre-and post-synaptic pulses. We demonstrate the features of the proposed synapse circuit with SPICE simulations, and validate its learning properties with high-level behavioral network simulations which use a stochastic gradient descent learning rule in two classification tasks.

Non-linear Memristive Synaptic Dynamics for Efficient Unsupervised Learning in Spiking Neural Networks

“…The former allows exploiting the full potential of memristive devices tuneability to achieve a real-time on-line adaptive operation. Among the spike-based training procedures, supervised learning rules inspired by the back-propagation exist (Urbanczik and Senn, 2014 ; Müller et al, 2017 ; Donati et al, 2019 ), which are seldom investigated for systems including realistic simulations of memristive devices (Nair et al, 2017 ; Payvand et al, 2018 ). On the contrary, the literature is extremely rich of reports dealing with networks trained by supervised (Brivio et al, 2019a ) and unsupervised versions of the so-called Spike Timing Dependent Plasticity (STDP) (Diehl and Cook, 2015 ; Garbin et al, 2015 ; Querlioz et al, 2015 ; Ambrogio et al, 2016 ; La Barbera et al, 2018 ).…”

A 4-Transistors/1-Resistor Hybrid Synapse Based on Resistive Switching Memory (RRAM) Capable of Spike-Rate-Dependent Plasticity (SRDP)

“…Integrated circuits capable of learning by STDP or SRDP rules generally require complicated, and large synaptic blocks hosting multiple transistors and capacitors [13], [14]. To enable small-area synapse, hence, high-density neural circuits, emerging memories such as resistive switching memory (RRAM) and phase change memory (PCM) have recently attracted a strong interest [15]- [26]. The development of RRAM-based SRDP synapses is still a major challenge for neuromorphic engineering [27]- [32].…”

Memristive and CMOS Devices for Neuromorphic Computing

“…Overlap-based implementations first require a pulse width of the order of time delays to allow for conductance change within the device, which results in pulses with a long duration causing a high power consumption. In addition to this, the need for long pulses to program overlap-based memristive devices also causes too slow signal processing in large neuromorphic networks, which leads to low throughput performance [166].…”