A 4-Transistors/1-Resistor Hybrid Synapse Based on Resistive Switching Memory (RRAM) Capable of Spike-Rate-Dependent Plasticity (SRDP)

Abstract

Mimicking the cognitive functions of the brain in hardware is a primary challenge for several fields, including device physics, neuromorphic engineering, and biological neuroscience. A key element in cognitive hardware systems is the ability to learn via biorealistic plasticity rules, combined with the area scaling capability to enable integration of high-density neuron/synapse networks. To this purpose, resistive switching memory (RRAM) devices have recently attracted a strong interest as potential synaptic elements. Here, we present a novel hybrid 4-transistors/1-resistor synapse capable of spike-rate-dependent plasticity. The frequency-dependent learning behavior of the synapse is shown by experiments on HfO 2 RRAM devices. Unsupervised learning, update, and recognition of one or more visual patterns in sequence is demonstrated at the level of neural network, thus, supporting the feasibility of hybrid CMOS/RRAM integrated circuits matching the learning capability in the human brain.

Toward a generalized Bienenstock-Cooper-Munro rule for spatiotemporal learning via triplet-STDP in memristive devices

“…There are two types of triplet-STDP in neuroscience: the first-spike-dominating model and last-spike-dominating model proposed by Froemke et al and Wang et al, respectively 41,42 . Progress has been made in emulating these two types of triplet-STDP using first-order and second-order memristors 36,[43][44][45] . However, the generalization from triplet-STDP to the BCM learning rule has not yet been experimentally demonstrated in memristors.…”

Modeling and Simulation of Spiking Neural Networks with Resistive Switching Synapses

“…In fact, these overlapping spikes cause a reset transition within RRAM device resulting in LTD at the synapse. Therefore, the operation principle of 4T1R synapse supports its ability to replicate SRDP rule implementing LTP at high f P RE and a noise-induced stochastic LTD at low f P RE [24,25].…”

“…Adapted with permission from [24]. Copyright 2016 IEEE plasticity in hardware, the combination of RRAM devices and field-effect transistors (FETs) serving as both cell selectors and current limiters has been widely used leading to the design of hybrid synaptic structures such as the one-transistor/one-resistor (1T1R) structure [23,24] and the four-transistors/one-resistor (4T1R) structure [24,25]. Figure 4.3 shows a circuit schematic where a hybrid structure based on serial connection of a Ti/HfO 2 /TiN RRAM cell and a FET, referred to as 1T1R structure, works as electronic synapse connecting a PRE to a POST with an integrate-and-fire (I&F) architecture.…”

“…b Measured and calculated resistance of 4T1R synapse for increasing f P RE supporting high-frequency synaptic potentiation. Adapted from [25] I&F stage, the generation of a fire pulse which is delivered at TE. As a result, overlap between spikes applied to M 1 gate, M 2 gate, and TE induces a set transition within RRAM device, namely LTP.…”

Memristive and CMOS Devices for Neuromorphic Computing

“…In SRDP, instead, the rate of spikes emitted by externally stimulated neurons dictates the potentiation or depression of the synapse, with high and low frequency stimulation leading to synaptic potentiation and depression, respectively [39]. Unlike STDP relying on pairs of spikes, SRDP has been attributed to the complex combination of three spikes (triplet) or more [40][41][42][43]. In addition to the ability to learn in an unsupervised way and emulate biological processes, SNNs also offer a significant improvement in energy efficiency thanks to the ability to process data by transmission of short spikes, hence consuming power only when and where the spike occurs [18].…”