Extended memory lifetime in spiking neural networks employing memristive synapses with nonlinear conductance dynamics

Abstract

Spiking neural networks (SNNs) employing memristive synapses are capable of life-long online learning. Because of their ability to process and classify large amounts of data in real-time using compact and low-power electronic systems, they promise a substantial technology breakthrough. However, the critical issue that memristor-based SNNs have to face is the fundamental limitation in their memory capacity due to finite resolution of the synaptic elements, which leads to the replacement of old memories with new ones and to a finite memory lifetime. In this study we demonstrate that the nonlinear conductance dynamics of memristive devices can be exploited to improve the memory lifetime of a network. The network is simulated on the basis of a spiking neuron model of mixed-signal digital-analogue sub-threshold neuromorphic CMOS circuits, and on memristive synapse models derived from the experimental nonlinear conductance dynamics of resistive memory devices when stimulated by trains of identical pulses. The network learning circuits implement a spike-based plasticity rule compatible with both spike-timing and rate-based learning rules. In order to get an insight on the memory lifetime of the network, we analyse the learning dynamics in the context of a classical benchmark of neural network learning, that is hand-written digit classification. In the proposed architecture, the memory lifetime and the performance of the network are improved for memristive synapses with nonlinear dynamics with respect to linear synapses with similar resolution. These results demonstrate the importance of following holistic approaches that combine the study of theoretical learning models with the development of neuromorphic CMOS SNNs with memristive devices used to implement life-long on-chip learning.

Stimulated Ionic Telegraph Noise in Filamentary Memristive Devices

“…Resistance dynamics driven by trains of identical pulses as those shown in Fig. 2a,b have been widely reported in the recent literature papers and most of them show a superimposed significant noise in the RESET transitions, as well 10–18 . Since these works are mainly aimed at demonstrating gradual or analogue transitions of RRAMs devices, the noise is rarely discussed.…”

“…Such programming scheme is intensively investigated for applications in hardware neural networks. As a matter of fact, in a large number of publications 10–18 also by other authors, the reported resistance evolution as a function of the number of identical pulses shows a large superimposed noise which is not contextually discussed and may be ascribed to STN. On the other side, we envision that the intentional activation of random resistance variations can be exploited for those applications relying on stochastic phenomena of nanoscaled devices, like random number generation 19–22 , physical unclonable function 23–25 , stochastic or chaos computing or emulation of stochastic cognitive neural processes 26–31 .…”

Spike‐Timing‐Dependent and Spike‐Shape‐Independent Plasticities with Dopamine‐Like Modulation in Nanocomposite Memristive Synapses

“…On the contrary, in spiking NS, it is possible to realize at least partially unsupervised learning, e.g., in terms of a spike-timing-dependent plasticity (STDP) mechanism. [30][31][32][33][34][35] Basic STDP is a local learning rule expressing a causal relationship between neurons. [36] STDP was shown to emerge naturally in different memristive devices.…”

A recipe for creating ideal hybrid memristive-CMOS neuromorphic processing systems

“…Even though it is clear that in real physical systems hard bounds are unavoidable (e.g., the supply rails in an electronic system), there is evidence that memristive devices exhibit soft bounds 76 . Therefore, by combining CMOS circuits with memristive devices, it is possible to design hybrid circuits that can implement and control the devices soft bounds for improving learning at the network level and for improving the overall system performance, e.g., in terms of reduced power consumption and increased memory capacity 45 . In contrast, it is impossible to precisely balance positive changes of synaptic weights with negative ones in hybrid memristive-CMOS neuromorphic computing systems.…”

“…In addition, to increase the memory-capacity of such a system by introducing soft bounds for the synaptic weights, it is necessary to provide a mechanism that can realize the desired state dependence in the synaptic weight-update transfer function 45 . This can be achieved by engineering the conductance change properties of the single memristive device, or by designing hybrid memristive-CMOS neuromorphic circuits interfaced with one or more memristive devices 11,79 .…”