We studied nitrogen incorporation in ultrathin oxynitride films by using oxygen and nitrogen radicals, and investigated the dependence of the electrical properties on the nitrogen profile. We found that the nitrogen position in the films could be controlled by using different processing sequences, and that the N concentration could be controlled at values up to 16%. In this process, the interface roughness depends on nitrogen position and nitrogen concentration: the interface roughness tends to increase as the N position close to the SiO2–Si interface and increase with N concentration. The results of an analysis of the electrical properties of these oxynitride films indicated that the best way to form the film was by radical nitridation after radical oxidation. These results show that the nitrogen position should be kept away from the SiO2–Si interface and nitrogen amount should be localized at the surface. Using this process, we have successfully achieved a low-leakage 1.5 nm oxynitride (equivalent oxide thickness) and maintained good device performance. This 1.5-nm-thick oxynitride has a leakage current two orders of magnitude less than that of 1.5-nm-thick SiO2 without decreasing the drain current. Radical oxynitridation should thus be very useful in making high-quality ultrathin gate-insulator films.
AbstractsThis work provides for the first time an experimental assessment of the impact of thermo-mechanically induced stresses by copper through-silicon vias, TSVs, on fully depleted Bulk FinFET devices. Both n and p type FinFETs are significantly affected by TSV proximity, exhibiting lower impact on drive current with respect to the planar devices. The obtained results are in agreement with the thermo-mechanical models for Cu-TSV and are supported by the 4 point bending stress calibration. Fig. 1: Cross sections of a through silicon via and a FinFET device at close proximity (a, b). The FinFET device has 40nm fin height, 20nm fin width, 1nm chemical oxide, followed by atomic layer deposition of 1.8nm HfO2 insulator and 5nm TiN work function metal gate (c,d)
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