Ultrathin EOT high-κ/metal gate devices for future technologies: Challenges, achievements and perspectives (invited)

Ragnarsson, Lars‐Åke; Chiarella, T.; Togo, M.; Schram, T.; Absil, P.; Hoffmann, T.

doi:10.1016/j.mee.2011.03.121

Cited by 60 publications

(41 citation statements)

References 9 publications

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“…32. It was also found that the initial growth condition of the interfacial layer affected the EOT scaling [84] and that may be explained satisfactorily the model given in Fig. 32 also.…”

Section: Lanthanum Oxide/silicon Interfacesupporting

confidence: 71%

“…If the sample was further covered with an additional polysilicon layer, the silicate layer was the thinnest and the effective k value could read 16. These experiments suggested that the EOT improvements should not be due to the interface layer scavenging [84]. The final polysilicon layer should not involve in any scavenging reaction at all.…”

Section: Lanthanum Oxide/silicon Interfacementioning

confidence: 97%

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On the scaling of subnanometer EOT gate dielectrics for ultimate nano CMOS technology

Wong

Iwai

2015

Microelectronic Engineering

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“…32. It was also found that the initial growth condition of the interfacial layer affected the EOT scaling [84] and that may be explained satisfactorily the model given in Fig. 32 also.…”

Section: Lanthanum Oxide/silicon Interfacesupporting

confidence: 71%

Section: Lanthanum Oxide/silicon Interfacementioning

confidence: 97%

On the scaling of subnanometer EOT gate dielectrics for ultimate nano CMOS technology

Wong

Iwai

2015

Microelectronic Engineering

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“…1c, EOT 0.42 nm) (6,7), or via in situ physical vapor deposition (PVD) of metals and Si onto the gate dielectric (Fig. 1d, EOT 0.45 nm) (8,9).…”

Section: Si Channel Interface Control: Direct and Remote Oxygen Scavementioning

confidence: 99%

(Invited) Gate Stacks for Silicon, Silicon Germanium, and III-V Channel MOSFETs

Frank¹,

Zhu²,

Bedell³

et al. 2014

ECS Trans.

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High-k gate dielectrics such as HfO 2 and metal gates such as TiN have been deployed across a wide range of silicon-based CMOS logic products. In some gate-first technologies, SiGe channels (cSiGe) have been implemented simultaneously for threshold voltage control in p-channel metal-oxide-semiconductor fieldeffect transistors (pMOSFET). Herein, we review aspects related to the impact of high-k/channel interfacial layers on Si, SiGe, and III-V gate stack quality and device performance. First, we review remote oxygen scavenging approaches for interfacial SiO 2 thinning in HfO 2 /Si nFET and HfO 2 /cSiGe pFET devices. We show that they allow equivalent oxide thickness (EOT) to be reduced to 0.4-0.5 nm, and we discuss device performance and reliability tradeoffs that may limit continued EOT scaling. For later technology nodes, high-carrier-mobility III-V semiconductors channels such as InGaAs are under consideration. We summarize three high-k/InGaAs channel interface approaches: Direct high-k deposition, Si capping, and InP capping.

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“…Overcoming the scaling limitations of SiO 2 -based/poly-Si gate stacks, CMOS scaling is further continued. The research on metal-oxides has focused on the scalability of Hf-based dielectric / metal-gate stacks with current oxide thicknesses of some tens of Angstroms [2,3]. Here, Atomic Layer Deposition (ALD) has found its way into the production due to the unique on-wafer and wafer-to-wafer uniformity and the atomic precision of the Hf-based metal-oxide deposition process [1].…”

Section: Introductionmentioning

confidence: 99%

Atomic layer deposition-based interface engineering for high-k/metal gate stacks

Östling

Henkel

Litta

et al. 2012

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology

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This review will discuss the in-situ surface engineering of active channel surfaces prior to or during the ALD high-k/metal gate deposition process. We will show that by carefully choosing ALD in-situ pre-treatment methods and precursor chemistries relevant electrical properties for future high-k dielectrics can be improved. Different high-k dielectrics such as Hafnium-Oxide (HfO 2 ), Aluminum-Oxide (Al 2 O 3 ), Lanthanum-Lutetium-Oxide (LaLuO 3 ) and Lanthanum-Oxide (La 2 O 3 ) for CMOS-based device technology are investigated in combination with Silicon (Si) and Germanium (Ge) substrates. Additionally, the use of ALD for deposition of a high-k dielectric gate stack on Graphene is discussed.

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Ultrathin EOT high-κ/metal gate devices for future technologies: Challenges, achievements and perspectives (invited)

Cited by 60 publications

References 9 publications

On the scaling of subnanometer EOT gate dielectrics for ultimate nano CMOS technology

On the scaling of subnanometer EOT gate dielectrics for ultimate nano CMOS technology

(Invited) Gate Stacks for Silicon, Silicon Germanium, and III-V Channel MOSFETs

Atomic layer deposition-based interface engineering for high-k/metal gate stacks

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