We introduce a new, to our knowledge, method using wavelets and probability theory for the evaluation of speckle interference patterns for quantitative out-of-plane deformation measurements of rough surfaces of nontransparent solids. The experiment uses a conventional Twyman-Green interferometer setup. The speckle interference patterns are obtained by the common method of subtraction of images taken before and after a surface deformation. The data are processed by a wavelet transformation, which analyzes the image structures on different length scales. Thus it is possible to separate the interference fringes from the noise. From the locations of the interference fringes, the deformation of the surface can be reconstructed by means of probability theory.
would not be achieved. As Cu-based technology becomes the mainstream metallization for the semiconductor industry, WL EM Wafer level electromigration behavior of copper and aluminum using technique will Play a much more important role for all Practical isothermal stress was investigated in this paper. Lifetime, lognormal Purposes. In this Paper, we rePo* and compare the WL EM testing standard deviation, and activation energy were evaluated as a results of both CU and AI using the WL isothermal (ISOT) technique. function of stress temperature as well as line width. Temperature The testing method keeps the test line at a Constant temperature dependence of the embedded 2D thermal behavior was modeled via by monitoring line resistance during test. The advantage, of this the initial stress current versus the initial resistance correlations. he method is that variations in the thermal conductance of the aanspofi mechanisms in the highly accelerated wafer level environment around the line due to variations in oxide thickness and elecfromigration were observed to be the same those in line cross sectional area are automatically accounted for, thus making moderately accelerated conventional package level electromirration ' control very accurate.-. . . .for both Cu-based and AI-based systems.
EXPERIMENTAL PROCEDURES : INTRODUCTION Electromigration (EM) performance of interconnect conductors inULSl microelectronic chips for the purpose of projecting lifetimes at use conditions is typically determined by strcssing.chips mounted in ceramic packages at high temperatures in an oven. In this arrangement, temperature and current density can .he varied independently. Limitations to this approach are 1) small sample size, 2) high cost, 3) package build time, and 4) extended test duration. Wafer level (WL) testing, in contrast, is performed on,a wafer probe station using current to supply both temperature and current acceleration. Stresses take only seconds or minutes instead of several hundred hours and sample sizes are generally larger. The major disadvantage to WL testing is that the temperature and current density cannot be controlled independently, and for this reason, little trust is placed in lifetime projections produced by this method. In addition to coupled parameters, several different types of WL tests are possible, and the results are different for each. These issues were addressed for AI-based technology [ 1,2].In today's advanced high performance technologies, the need for reduced resistance and capacitance interconnects has led to an evolution kom AI-based to Cu-based interconnect processes. Since the resistance of Cu wiring-is about 35% lower than AI and the melting point of Cu (1083T) is 423°C higher than AI (660"C), the EM performance of Cu is about 100 times bener than AI fiom the package level test reported by IBM [3]. It has become-an increasing challenge to obtain the necessary data for determining lifetime predictions and use conditions for each successive generation of Cubased technology by means of traditio...
The continued scaling of DRAM cell sizes requires maintaining a sufficiently high storage capacitance per cell. Capacitance enhancement technique using hemisphericalpolysilicon grains (HPG) in deep trench capacitors has been previously reported for the continued scaling of deep trench DRAM technology [l]. In this paper, the reliability aspects of such HPG deep trench capacitors are critically investigated. The operational lifetime, based on constant voltage stressing, demonstrates the feasibility of such capacitors for gigabit DRAM applications.
With high aspect ratio, tight spacing, small linewidtlis, and low supply voltages associated with the scaling of the DRAM cell, signal for thc sense amplificr becomcs wcaker for each new DRAM goneraiion. Wc have devdopcd a sigtial margin testing methodology capablc of idenlifying process sensitivities relevant to DRAM functionality and rcliabiliLy at low temperaturcs. This paper describcs the test methodology and discusses thc bciicfits derivcd from applying this mcthod to 256M DRAM product developmcnt. 6 99 IRW FINAL REPORT 0-78D3~5648~1~B01$10.00 "1B80 IEEE
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