In order to address NBTI degradation mechanism on With the decrease of the high-k layer thickness, NBTI high-k stacks, On The Fly measurements from -1.2V to -2V becomes more critical than PBTI. The relative contribution stress voltages with slow recovery at OV were conducted. of interface states and trapping on NBTI is analysed in HfAs detailed by Huard et al [6], linear relations between drain based stacks. Dit density and generation kinetics were found current and VT variations were beforehand extracted (Fig. to be similar to that in SiO2, whereas a very large fast 4). Afterward VT shifts were obtained from drain current trapping component was evidenced. The pre-existing traps measurement during CVS. Typical results for 2.5nm HfO2 responsible for this fast trapping effect were related to N dielectric are presented on Fig. 5. incorporation in the interfacial layer after TiN PVD deposition. Finally, a significant lifetime improvement is Interface degradation during NBTI stress achieved using TaC as gate material. Fig. 6 shows the good agreement between CV measurements on 2.5nm HfO2 during NBTI stress and Introduction simulation considering a constant Dit level in the bandgap, PBTI and NBTI in high-k/metal gate stacks are known to which is representative of Pb centers generation at the be key reliability issues. Initially PBTI in high-k dielectrics Si/SiO2 interface. was considered to be more critical than NBTI insofar as In order to further address the interface states generation, strong electron trapping occurred during PBTI stress in preslow recovery was confronted with the model proposed by existing traps identified as 0 vacancies in the high-k layer Huard et al for SiO2 dielectric [6,7]. Based on the universal [1,2]. But recent studies have shown that PBTI is strongly recovery law [8], by extrapolating recovery data, Dit reduced in thin high-k films (<2nm) and that the BTI generation is approximated by: lifetime of the transistors may also be controlled by NBTI = x exp( n)x degradation [3]. If the role played by the high-k insulator in D1t (EoX t) Ap kT NBTI has been already investigated [3][4][5], the impact of the with AP = KxE VP gate electrode still remains unknown. ox In this paper we address NBTI issue in high-k/TiN stacks. First, interface states generation is assessed by modelling Especially, the density of Dit and their generation and standard charge pumping. Then, pulse Id-Vg dynamics are described by this model through Ap and n measurements are used to analyse fast trapping effect. The parameters. impact of dielectric and gate material is finally discussed. Regardless of the stress voltage, good agreement with the model was obtained; n and Ap values are presented on Fig. 7 Experimental with respect to stress oxide field. It turns out that, at a fixed Transistors have been processed using a conventional oxide field, Dit density and the generation kinetics in high-k CMOS process on Si (100) 300mm substrates. 2.5 nm HfO2 dielectrics are the same as in SiO2 reference. Besides n and and, 2.5nm and 3nm...
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