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23Two different experiments were carried out to evaluate three insecticides. In the 24 first one, the effect of two insecticides, methomyl and indoxacarb, on pupae and 25 adults of the whitefly Bemisia tabaci (Gennadius) parasitoid Eretmocerus mundus 26Mercet was evaluated under laboratory and greenhouse conditions, using sweet 27 pepper (Capsicum annuum L.) plants. In the second experiment, oxamyl was 28 tested to study its effect on the ability of E. mundus to parasitize and control B. 29 tabaci in sweet pepper plants, using a greenhouse cage evaluation. Methomyl and 30 indoxacarb caused low mortality of E. mundus pupae (17.6 and 7.8% 31 respectively), although methomyl mortality was significantly higher. Methomyl 32 produced 100% mortality on E. mundus adults with fresh and 24 hour-old 33 residues on leaves, significantly higher than the mortality produced by indoxacarb 34 (values ranged from 43.9 to 34.4%). The harmful effect of methomyl persisted for 35 a long time (up to 60 days). The results of the experiment with oxamyl showed 36 that E. mundus controlled whitefly population, without significant interaction 37 between the presence of the parasitoid and insecticide on whitefly mortality. 38Whitefly mortality in the presence of the parasitoid was 87.8%, significantly higher 39 than the mortality in the absence of E. mundus (59.3%). Oxamyl did not produce 40 a significant effect on the emergence of E. mundus adults. Application of the 41 products in IPM programs is discussed. 42 43

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The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the Degradation Delay Model presented in previous papers with a new algorithm to handle the inertial effect, and is able to take account of the propagation and filtering of arbitrarily narrow pulses (glitches, etc.). The model clearly overcomes the limitations of conventional approaches.

Abstract. This contribution extends the Degradation Delay Model (DDM), previously developed for CMOS inverters, to simple logic gates. A gate-level approach is followed. At a first stage, all input collisions producing degradation are studied and classified. Then, an exhaustive model is proposed, which defines a set of parameters for each particular collision. This way, a full and accurate description of the degradation effect is obtained (compared to HSPICE) at the cost of storing a rather high number of parameters. To solve that, a simplified model is also proposed maintaining similar accuracy but with a reduced number of parameters and a simplified characterization process. Finally, the complexity of both models is compared.

Abstract. In previous papers we have presented a very accurate model that handles the generation and propagation of glitches, which makes an important headway in logic timing simulation. This model is called Delay Degradation Model (DDM). Characterizing DDM completely also implies the characterization of the normal propagation delay. In this paper, we propose a simple heuristic model that includes its dependence on the output load and the input transition time. We have tested this model and found a mean deviation lower than 4%. Also, we present a characterization process for this model that is fully integrated into AUTODDM without affecting the total simulation time needed to characterize a standard cell.

Abstract. This communication shows the influence of clocking schemes on the digital switching noise generation. It will be shown how the choice of a suited clocking scheme for the digital part reduces the switching noise, thus alleviating the problematic associated to limitations of performances in mixed-signal Analog/Digital Integrated Circuits. Simulation data of a pipelined XOR chain using both a single-phase and a two-phase clocking schemes, as well as of two nbit counters with different clocking styles lead, as conclusions, to recommend multiple clock-phase and asynchronous styles for reducing switching noise.