Simple binary random number generator

Bellido, M.J.; Acosta, Antonio; Valencia, M.; Barriga, A.; Huertas, J.L.

doi:10.1049/el:19920389

Cited by 26 publications

(15 citation statements)

References 5 publications

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“…Bellido et al [17] presented a method to generate true random numbers from the metastability of an RS latch. The circuit was designed and implemented with close attention; e.g., a dedicated initialization clock was adopted to precharge and discharge internal nodes.…”

Section: Preceding Studies On Metastability-based Trngsmentioning

confidence: 99%

FPGA Implementation of Metastability-Based True Random Number Generator

Hata

Ichikawa

2012

IEICE Trans. Inf. & Syst.

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SUMMARYTrue random number generators (TRNGs) are important as a basis for computer security. Though there are some TRNGs composed of analog circuit, the use of digital circuits is desired for the application of TRNGs to logic LSIs. Some of the digital TRNGs utilize jitter in freerunning ring oscillators as a source of entropy, which consume large power. Another type of TRNG exploits the metastability of a latch to generate entropy. Although this kind of TRNG has been mostly implemented with fullcustom LSI technology, this study presents an implementation based on common FPGA technology. Our TRNG is comprised of logic gates only, and can be integrated in any kind of logic LSI. The RS latch in our TRNG is implemented as a hard-macro to guarantee the quality of randomness by minimizing the signal skew and load imbalance of internal nodes. To improve the quality and throughput, the output of 64-256 latches are XOR'ed. The derived design was verified on a Xilinx Virtex-4 FPGA (XC4VFX20), and passed NIST statistical test suite without post-processing. Our TRNG with 256 latches occupies 580 slices, while achieving 12.5 Mbps throughput.

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Section: Preceding Studies On Metastability-based Trngsmentioning

confidence: 99%

FPGA Implementation of Metastability-Based True Random Number Generator

Hata

Ichikawa

2012

IEICE Trans. Inf. & Syst.

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“…The large negative feedback forces the output of the inverters to an intermediate voltage, close to halfway between logic levels. Flipping the switches to activate the bi-stable configuration at an intermediate voltage often forces metastability [10], [11]. The final state achieved under these conditions is shown to be unpredictable if the initial conditions of the bi-stable circuit are at intermediate voltages.…”

Section: Circuit Detailsmentioning

confidence: 99%

“…We present a random number generator comprised entirely of digital circuits, which utilizes electronic noise. Unlike earlier work [11], only standard digital gates without regard to precise layout were used. …”

mentioning

confidence: 99%

Design and Implementation of a True Random Number Generator Based on Digital Circuit Artifacts

Epstein

Hars

Krasinski

et al. 2003

Lecture Notes in Computer Science

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Abstract. There are many applications for true, unpredictable random numbers. For example the strength of numerous cryptographic operations is often dependent on a source of truly random numbers. Sources of random information are available in nature but are often hard to access in integrated circuits. In some specialized applications, analog noise sources are used in digital circuits at great cost in silicon area and power consumption. These analog circuits are often influenced by periodic signal sources that are in close proximity to the random number generator. We present a random number generator comprised entirely of digital circuits, which utilizes electronic noise. Unlike earlier work [11], only standard digital gates without regard to precise layout were used.

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“…The earliest solutions, which were based on latches and flip-flops, appeared in [21], [22]. SRAM start-up values were first used as a source of entropy in [5].…”

mentioning

confidence: 99%

Improved Generation of Identifiers, Secret Keys, and Random Numbers From SRAMs

Baturone

Prada-Delgado

Eiroa³

2015

IEEE Trans.Inform.Forensic Secur.

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Abstract-This paper presents a method to simultaneously improve the quality of the identifiers, secret keys, and random numbers that can be generated from the start-up values of standard Static Random Access Memories, SRAMs. The method is based on classifying memory cells after evaluating their startup values at multiple measurements in a registration phase. The registration can be done without unplugging the device from its application context, and with no need for a complex laboratory setup. The method has been validated experimentally with standard low-power SRAM modules in two different Application Specific Integrated Circuits, ASICs, fabricated with 90-nm TSMC technology. The results show that with a simple registration the length of the identifiers can be reduced by 45%, worst-case bit error probability (which defines the complexity of the error correcting code needed to recover a secret key) can be reduced by 64%, and the worst-case minimum entropy value is improved, thus reducing the number of bits that have to be processed to obtain full entropy by 81%. The method can be applied to standard digital designs by controlling the external power supply to the SRAM using software or by incorporating simple circuitry in the design. In the latter case, a module for implementing the method in an ASIC designed in 90-nm TSMC technology occupies an active area of 42,025 μm 2 .

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Simple binary random number generator

Cited by 26 publications

References 5 publications

FPGA Implementation of Metastability-Based True Random Number Generator

FPGA Implementation of Metastability-Based True Random Number Generator

Design and Implementation of a True Random Number Generator Based on Digital Circuit Artifacts

Improved Generation of Identifiers, Secret Keys, and Random Numbers From SRAMs

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