Design and Implementation of a True Random Number Generator Based on Digital Circuit Artifacts

Epstein, Michael A.; Hars, Laszlo; Krasinski, Raymond; Rosner, Martin Christopher; Zheng, Huiyong

doi:10.1007/978-3-540-45238-6_13

Cited by 66 publications

(49 citation statements)

References 9 publications

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“…The jitter can be extracted by means of a sampling unit, triggered by a reference clock, which can be an external clock signal or the output from another ring oscillator. This simple structure, which in this paper, we call an elementary true random number generator (elementary TRNG), and the underlying physical phenomena are widely reported in the literature, since the elementary TRNG is often used as a building block for on-chip TRNGs [4], [3], [15]. There are two classical ways to describe the jitter of a clock signal either as a edgeto-edge jitter or a edge-to-reference jitter: in the first approach, the edge timing is referenced to the preceding edge (period jitter) or to the N th -preceding (N -period jitter), while in the other approach, the edge position is referenced to a separate reference signal (see [11, p. …”

Section: Introductionmentioning

confidence: 99%

Towards an Oscillator Based TRNG with a Certified Entropy Rate

Lubicz¹,

Bochard

2015

IEEE Trans. Comput.

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Abstract-We describe a practical and efficient method to determine the entropy rate of a TRNG based on free running oscillators that does not require outputting and analyzing the clock signals with external equipment. Rather it relies on very simple computations that can be embedded in any logic device such as FPGA or ASIC. The method can be used for the calibration of an oscillator based TRNG or for on-line certification of its entropy rate. Our approach, which is inspired by the coherent sampling method, works under the general assumption that the period jitter is small compared to the period of the generated clock signal. We show that, in this case, it is possible to measure the relative phase between clocks of two oscillators with far higher precision than the time resolution given by the period of any internal clock signal. We use this observation to recover, under some reasonable heuristics, the distribution of the random walk component of the jitter, from which it is possible to compute a lower bound of the entropy rate of the TRNG. Our method was thoroughly tested in simulations and in hardware. At the end of the paper, we draw some conclusions and make recommendations for a reliable implementation of TRNGs in cryptographic applications.

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Section: Introductionmentioning

confidence: 99%

Towards an Oscillator Based TRNG with a Certified Entropy Rate

Lubicz¹,

Bochard

2015

IEEE Trans. Comput.

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“…The phase jitter of a ring oscillator is then extracted by means of a sampling unit, for instance a type-D flip-flop triggered by another ring oscillator or by an external clock signal. This simple structure has been widely studied in the literature as a building block for many on-chip TRNGs [8,3,14]. This paper aims to present a comprehensive statistical model of such a basic random unit, and contribute more generally to improving the security analysis of hardware random number generators.…”

Section: Introductionmentioning

confidence: 99%

On the Security of Oscillator-Based Random Number Generators

Baudet

Lubicz

Micolod³

et al. 2010

J Cryptol

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Abstract. Physical random number generators (a.k.a. TRNGs) appear to be critical components of many cryptographic systems. Yet, such building blocks are still too seldom provided with a formal assessment of security, in comparison to what is achieved for conventional cryptography. In this work, we present a comprehensive statistical study of TRNGs based on the sampling of an oscillator subject to phase noise (a.k.a. phase jitters). This classical layout, typically instantiated with a ring oscillator, provides a simple and attractive way to implement a TRNG on a chip. Our mathematical study allows one to evaluate and control the main security parameters of such a random source, including its entropy rate and the biases of certain bit patterns, provided that a small number of physical parameters of the oscillator are known. In order to evaluate these parameters in a secure way, we also provide an experimental method for filtering out the global perturbations affecting a chip and possibly visible to an attacker. Finally, from our mathematical model, we deduce specific statistical tests applicable to the bit stream of a TRNG. In particular, in the case of an insecure configuration, we show how to recover the parameters of the underlying oscillator.

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“…Embedded TRNGs frequently use some external devices or rather heuristic source of randomness (e.g. metastability [5]). Although these limitations can be overcome by a design of proper custom circuits, randomness extraction is still a big challenge in the designs based on off the shelf devices as FPGA [6], [7] or general microprocessors [8].…”

Section: Introductionmentioning

confidence: 99%