Logical modelling of delay degradation effect in static CMOS gates

Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)

“…The type of input collision that more notably affects the behaviour of digital circuits are the glitch collisions, or those that may cause narrow pulses or glitches. In previous papers [6][7][8] we have presented a very accurate model that handles the generation and propagation of glitches, which makes an important headway in logic-timing simulation. This model is called Delay Degradation Model (DDM).…”

Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level

“…In mixed-signal circuits, switching activity of the digital part creates a switching noise that is transferred to the analog part [3,4,5]. Furthermore, as digital circuits become faster and larger, the influence of glitches in the switching activity grows because there are more and more input collisions [6,7,8,9]. Thus, evaluation of switching activity is today a major topic in the design process of both pure digital, and mixed-signal integrated circuits.…”

Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level

“…The algorithm is integrated as part of the HALOTIS logic timing simulator [7], so it inherits benefits of the event-driven technique (fast simulation) and of the accurate delay models it implements. Regarding the delay model, HALOTIS uses the Degradation Delay Model (DDM) which provides with a very accurate and efficient way to handle the generation and propagation of glitches [8,9,10,11]. This property is of special interest in this work, since these glitches contributes an important part of the switching activity and hence the average current [12].…”