Degradation Delay Model Extension to CMOS Gates

Abstract

Abstract. This contribution extends the Degradation Delay Model (DDM), previously developed for CMOS inverters, to simple logic gates. A gate-level approach is followed. At a first stage, all input collisions producing degradation are studied and classified. Then, an exhaustive model is proposed, which defines a set of parameters for each particular collision. This way, a full and accurate description of the degradation effect is obtained (compared to HSPICE) at the cost of storing a rather high number of parameters. To solve that, a simplified model is also proposed maintaining similar accuracy but with a reduced number of parameters and a simplified characterization process. Finally, the complexity of both models is compared.

Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)

“…The type of input collision that more notably affects the behaviour of digital circuits are the glitch collisions, or those that may cause narrow pulses or glitches. In previous papers [6][7][8] we have presented a very accurate model that handles the generation and propagation of glitches, which makes an important headway in logic-timing simulation. This model is called Delay Degradation Model (DDM).…”

“…This information is necessary to be able to reproduce simulation results by others and also to check the viability of the approach: a model that is very hard or expensive to characterize may be useless. In previous papers [8,9] we have described the characterization process of the degradation parameters of DDM and we have presented a tool that automates the process, called AUTODDM.…”

Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level

“…The algorithm is integrated as part of the HALOTIS logic timing simulator [7], so it inherits benefits of the event-driven technique (fast simulation) and of the accurate delay models it implements. Regarding the delay model, HALOTIS uses the Degradation Delay Model (DDM) which provides with a very accurate and efficient way to handle the generation and propagation of glitches [8,9,10,11]. This property is of special interest in this work, since these glitches contributes an important part of the switching activity and hence the average current [12].…”

HALOTIS: High Accuracy Logic TIming simulator with inertial and degradation delay model

“…In such a case, the pulse is considered to be degraded. We showed in [15,16,17] that the delay decreases exponentially as pulses are shortened. Full degradation effect insights were studied for the case of CMOS gates and a delay model that takes into account the exponential behavior of the degradation effect was also presented.…”

“…In [14,15,16,17] a new model denominated Inertial and Degradation Delay Model (IDDM) has been introduced. This model combines the degradation effect of glitches with a new algorithm to handle the inertial effect.…”