Young's modulus and the fracture strength of thick polysilicon films were evaluated with surface micromachined test structures. The polysilicon films were deposited in an epitaxial reactor and were about 10.5 µm thick. Four different processing schemes of doping and annealing were used and thus four different sets of test structures were micromachined. A micromanipulator system developed at Uppsala University was used to make tensile tests. The micromanipulator is adapted to a scanning electron microscopy environment and all tests were done in situ so that the testing procedure could be monitored at high magnification. From the tensile tests Young's modulus as well as the mean fracture strength and Weibull modulus of each of the films were evaluated. Young's modulus was also evaluated from the collapse voltage of test structures consisting of an electrostatically movable plate suspended by springs. Film texture measurements by x-ray diffraction and cross sectional transmission electron microscopy revealed that the silicon grains had preferential orientations. A mean value of Young's modulus of the film was calculated based on the Young's modulus values of the preferred orientations. It was found that Young's modulus of polysilicon evaluated by the three methods presented agree with each other as well as with other reliable data.

No abstract

No abstract

We describe a simple, low cost process, suitable for fabrication of low-voltage sub-l/4micron CMOS devices, utilizing Wpolycide dual-gate structure. The novel feature of this process is a low gate stack profile (150-200nm), made possible by implanting dopants directly into tungsten silicide. The threshold voltage shifts due to lateral dopant diffusion between P-and NMOS devices with connected gates are minimized (<30mV) by combining thermal treatments with selective nitrogen gate co-implant to control dopant activation and diffusion. Both Pand NMOS devices have excellent Ion/Ioff characteristics, low leakage currents, good short channel behavior and low gate sheet resistance of 8-10&2/D .

Radiative isoelectronic impurity complexes consisting of pairs of Be atoms that bind excitons can be formed in both Si and SiGe/Si superlattices during growth by molecular beam epitaxy. We describe in this letter the conditions under which these radiative complexes can be formed, show that they can be localized in the alloy layers of a superlattice, and demonstrate that the blueshift of the bound-exciton’s no-phonon line that occurs for Be-implanted superlattices is absent for grown-in Be complexes. Be densities in excess of 5×1017 cm−3 can be achieved.

No abstract

Electrical characterization of MOS structures and device modeling require accurate information about dopant concentration, particularly at the poly-Si/SiO2 interface. We compare four experimental techniques (secondary ion mass spectrometry SIMS, resonant ion mass spectrometry RIMS, differential Hall effect profiling, and spreading resistance analysis) to measure boron and free carrier concentrations in poly-Si, SiO2 and crystalline Si. We find that no single technique completely characterizes the entire MOS structure, and that spreading resistance analysis in particular substantially underestimates the free carrier concentration at the poly-Si/SiO2 interface. We conclude that in most cases of technological interest the magnitude of the poly depletion effect scales with the average carrier concentration at some distance away from the interface and that the interfacial effects, such as dopant segregation, are of only secondary importance. These findings are supported by theoretical modeling of capacitance-voltage behavior of boron-doped MOS capacitors.

Deep submicron CMOS technology for low-power, low-voltage applications requires the use of symmetric n+/p+ poly gate structures. This requirement introduces a number of processing challenges, involving fundamental issues of atomic diffusion over distances of 1Å to ∼30μm. Two of the critical issues are dopant cross-diffusion between P- and NMOS devices with connected gates, resulting in large threshold voltage shifts, and boron penetration through the gate oxide. We show that in devices with W-polycide dual-gat:e structure most of these problems can be alleviated by using rapid thermal annealing, RTA, in combination with a few additional, simple processing steps (e. g., low-temperature recrystallization of a-Si layer and selective nitrogen coimplants). The RTA step, in particular, ensures thai: the boron activation in the p+ poly-Si remains high and negates any effects of arsenic cross-diffusion. CMOS devices with properly processed gates have low gate stack profiles, small threshold voltage shifts (<30mV), and excellent device characteristics.