Metal-organic chemical vapor deposition growth of GaAs on Si was studied using the selective aspect ratio trapping method. Vertical propagation of threading dislocations generated at the GaAs∕Si interface was suppressed within an initial thin GaAs layer inside SiO2 trenches with aspect ratio >1, leading to defect-free GaAs regions up to 300nm in width. Cross-sectional and plan-view transmission electron microscopies were used to characterize the defect reduction. Material quality was confirmed by room temperature photoluminescence measurements. This approach shows great promise for the fabrication of optoelectronic integrated circuits on Si substrates.

We report on the metallorganic chemical vapor deposition growth of GaAs on patterned Si (001) substrates, which utilizes the aspect ratio trapping method. It was found that when growing GaAs above the SiO2 trenched region, coalescence-induced threading dislocations and stacking faults originated on top of the GaAs/SiO2 interfaces. These defects were found to be indirectly related to the initial defect-trapping process during trenched GaAs growth. Causes of coalescence defect formation and its reduction were experimentally investigated by employing a two-step growth optimization scheme. Improvement of material quality has been characterized by cross-sectional and plan-view transmission electron microscopy and x-ray diffraction.

Thin crystalline silicon solar cells have the potential to achieve high efficiency due to the potential for increased voltage. Thin silicon wafers are fragile; therefore, means of support must be provided. This paper reports the design, development, and analysis of an 18-μm crystalline silicon solar cell electrically integrated with a steel alloy substrate. This ultrathin silicon is epitaxially grown on porous silicon and then transferred onto the steel substrate. This method allows the independent processing of each surface. The steel substrate enables robust handling and provides a conductive back plane. Three groups of cells with planar and textured structures are compared; significant improvements in J sc , V o c , and fill factor (FF) are achieved. The best cell shows an efficiency of 16.8% with an open-circuit voltage of 632 mV and a short-circuit current density of 34.5 mA/cm 2 .

High quality InP thin films have been demonstrated in SiO2 trenches on silicon via Aspect Ratio Trapping (ART), whereby defects arising from lattice mismatch (~8%) are trapped by laterally confining sidewalls. Double-buffer layers and two-step ART growth processes have been employed to trap vertical threading dislocations originating at InP/Si interface. InP film quality and optical properties have been analyzed using SEM, TEM and room temperature photoluminescence. Full trapping of dislocations has been demonstrated for trenches up to 400 nm in width without the additional formation of defects at the sidewalls above 500 nm initial growth. This approach shows great promise for the integration of III-V materials onto silicon.

High quality GaAs epilayers grown by metal-organic chemical vapor deposition are demonstrated on a SiO 2-patterned silicon substrate using aspect ratio trapping technique, whereby threading dislocations from lattice mismatch are largely reduced via trapping in SiO 2 trenches during growth. A depletion-mode metal-oxide-semiconductor field-effect transistor ͑MOSFET͒ is demonstrated on a n-doped GaAs channel with atomic-layer deposited Al 2 O 3 as the gate oxide. The 10 m gate length transistor has a maximum drain current of 88 mA/mm and a transconductance of 19 mS/mm. The surface mobility estimated from the accumulation drain current has a peak value of ϳ500 cm 2 / Vs, which is comparable with those from previously reported depletion-mode GaAs MOSFETs epitaxially grown on semi-insulating GaAs substrates.