The structure of hydrogenated silicon (Si:H) films deposited by rf and dc plasma process on Si (100) and (111) wafers is correlated with the surface passivation quality and heterojunction cell performance. Microstructural defects associated with SiH2 bonding and apparent ion bombardment in dc plasmas have little or no adverse effect on passivation or cell properties, while presence of crystallinity in Si:H i layer severely deteriorates surface passivation and cell open circuit voltage (Voc). Excellent surface passivation (lifetime of >1ms) and high efficiency cells (>18%) with Voc of 694mV are demonstrated on n-type textured Czochralski wafer using dc plasma process.
The search for an ideal surface passivation layer of crystalline silicon (c-Si) to be employed in a silicon heterojunction photovoltaic device has garnered much attention. The leading candidate is a few nanometers of intrinsic amorphous silicon ((i)a-Si:H) film. Reported dependencies of film surface passivation quality on substrate preparation, orientation, and deposition temperature have been extended in this work to include H2 to SiH4 dilution ratio and postdeposition annealing. Simple avoidance of the deposition regimes that lead to epitaxial growth of Si on the c-Si substrate produces decent lifetimes on the order of 500μs. Subsequent low temperature annealings cause an important restructuring of Si–H bonding at the a-Si:H∕c-Si interface increasing the amount of monohydride at the c-Si surface. This restructuring would reduce the c-Si surface defect density and cause an improvement of surface passivation as confirmed by effective lifetime measurements. Final effective carrier lifetimes up to 2550μs are achieved postannealing. Initial results indicate the improvement depends on surplus SiH2 from the interface region.
Heterostuctures of amorphous silicon (a-Si:H) and ntype crystalline silicon (c-Si) were investigated with special emphasis on the effect of emitter [p (a-Si:H)] and buffer layer [i (a-Si:H)] processing conditions. Boron (B)-doping in emitter layer sensitively affects performance of heterojunction solar cells without a buffer layer and controls valence band offset (DEv) at the hetero-interface. Insertion of 10 nm buffer layers passivate c-Si surface very efficiently albeit with an increased DEv and poor carrier transport across the heterojunction. Consequently, an open circuit voltage (Voc) of 700 mV was achieved with low fill factor (FF). Buffer layers deposited at high H2/SiH4 ratio (R=40) and/or at higher temperature (300°C) improve FF (77%) but lead to lower Voc (638 mV). Therefore, the emitter and the buffer layer process parameters play important roles to determine the band alignment and carrier transport across the a-Si:H / c-Si hetero-interface.
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