In this paper, it is shown that self-heating causes a gigantic effect on the capacitances of MOSFETs/FinFETs. The effect is used to determine the SOI FinFET thermal impedance and to determine the temperature rise during FinFET operation. IntroductionFinFETs are regarded as prospective replacements for bulk-CMOS devices beyond the 22-nm node. Due to the poor thermal conductivity of some of the materials used in FinFET fabrication, and due to the confined nature of the FinFET geometry, self-heating is expected to be more significant in FinFETs than in their bulk-CMOS counterparts, affecting not only device performance, but also NBTI and oxide reliability [1,2]. To the best of the authors' knowledge, all studies on FinFET self-heating so far are based on simulations [1,3,4], and experimental assessment is lacking. In this paper, we will (i) show that self-heating causes a gigantic effect on the capacitances C DD and C DG , (ii) use that effect as an ultra-sensitive method to extract the frequency-dependent complex thermal impedance Z th (f ), and (iii) determine the temperature rise in our SOI FinFETs and its impact on the device performance.

No abstract

http://www.gianlucafiori.org/articles/SSE09.pd

This paper presents the results of a comparison among five Monte Carlo device simulators for nano-scale MOSFETs. The Monte Carlo models are applied to the simulation of the I-V characteristics of a 25 nm gate-length MOSFET representative of the highperformance transistor of the 65 nm technology node. Appreciable differences between the simulators are obtained in terms of simulated I ON . These differences are mainly related to different treatments of the ionized impurity scattering (IIS) and pinpoint a limitation of the available models for screening effects at very large carrier concentrations.