Abstract:This paper presents the results of a comparison among five Monte Carlo device simulators for nano-scale MOSFETs. The Monte Carlo models are applied to the simulation of the I-V characteristics of a 25 nm gate-length MOSFET representative of the highperformance transistor of the 65 nm technology node. Appreciable differences between the simulators are obtained in terms of simulated I ON . These differences are mainly related to different treatments of the ionized impurity scattering (IIS) and pinpoint a limitat… Show more
“…Considering now MC models, which take into account more accurately the quasi-ballistic nature of carrier transport in short MOSFETs, the mutual agreement is quite satisfactory, much better of what has been found in [18], mainly because in the 32 nm FDSOI device considered in this work the role of II scattering in the S/D regions is significantly reduced with respect to the devices in [18]. It is also interesting to note that different treatments of quantization (MSMC vs. quantum corrections vs. no quantization) and of different descriptions of the band-structure (full-band vs. simple non-parabolic analytical bands) only have a marginal impact on the simulated current of this device.…”
Section: Drain Current In the 32 Nm Templatesupporting
confidence: 55%
“…Examples of this methodology are [15][16][17][18], works that, in our opinion, have increased the awareness and the confidence of the electron device community in the capabilities of device modeling.…”
Section: Introductionmentioning
confidence: 97%
“…In this paper we have followed an approach similar to the one in [15][16][17][18]. We have first defined template (idealized) devices: a 32 nm Fully-Depleted-SOI (FDSOI) and a 22 nm Double-Gate (DG) device, both optimized for low-stand-by-power applications.…”
“…Considering now MC models, which take into account more accurately the quasi-ballistic nature of carrier transport in short MOSFETs, the mutual agreement is quite satisfactory, much better of what has been found in [18], mainly because in the 32 nm FDSOI device considered in this work the role of II scattering in the S/D regions is significantly reduced with respect to the devices in [18]. It is also interesting to note that different treatments of quantization (MSMC vs. quantum corrections vs. no quantization) and of different descriptions of the band-structure (full-band vs. simple non-parabolic analytical bands) only have a marginal impact on the simulated current of this device.…”
Section: Drain Current In the 32 Nm Templatesupporting
confidence: 55%
“…Examples of this methodology are [15][16][17][18], works that, in our opinion, have increased the awareness and the confidence of the electron device community in the capabilities of device modeling.…”
Section: Introductionmentioning
confidence: 97%
“…In this paper we have followed an approach similar to the one in [15][16][17][18]. We have first defined template (idealized) devices: a 32 nm Fully-Depleted-SOI (FDSOI) and a 22 nm Double-Gate (DG) device, both optimized for low-stand-by-power applications.…”
“…This mechanism is expected to influence the resulting current since it increases the resistance of the source/drain extentions, but in this paper we focus on the transport along the intrinsic channel. Notice that the treatment of ionized impurity scattering is still an issue even when considering 3Deg-MC models [13].…”
“…To limit this resistive behavior of the access regions, a possible solution is to increase doping levels up to a few 10 20 cm -3 . The study of transport in these ultra-thin and highly doped regions is a very challenging problem in device modeling [3]. Simulations have to accurately take into account all together vertical confinement, non-stationary transport, degeneracy and all relevant scattering mechanisms [4].…”
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