Simulation of self-heating effects in different SOI MOS architectures

Braccioli, M.; Curatola, G.; Yang, Yiqun; Sangiorgi, E.; Fiegna, Claudio

doi:10.1016/j.sse.2008.09.020

Cited by 40 publications

(20 citation statements)

References 15 publications

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“…However, one should remember that first, the present devices feature not only thin‐BOX but also a thinned down Si film, thus strongly degrading its thermal conductivity, and second, channel lengths are significantly reduced. Then, our results are in fairly good agreement with simulation predictions for UTB MOSFETs reported in . It would be interesting to point out that although the temperature rise in the device is only ~15 K in the low power range (i.e., targeting low‐power applications), the degradation of the output conductance may be very significant (for V g in moderate inversion), especially considering the relative g d variation with respect to its low‐frequency value (up to 100%).…”

Section: Self‐heating Effectssupporting

confidence: 86%

“… performed electro‐thermal simulations to study the dependence of FinFET thermal properties on BOX thickness, source and drain extensions length, fin spacing, and fin height. However, analysis of the thermal properties in is not supported by experimental results and is entirely based on numerical simulations that require certain assumptions about heat conduction paths, device symmetries, and boundary conditions. Experimental work on self‐heating in FinFETs and UTBBs was carried out, respectively in and in .…”

Section: Self‐heating Effectsmentioning

confidence: 99%

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Silicon‐on‐insulator MOSFETs models in analog/RF domain

Raskin

2013

Int J Numerical Modelling

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SUMMARYSeveral physical phenomena specific to silicon-on-insulator metal-oxide-semiconductor field-effect transistors, such as floating body effects, self-heating, and substrate coupling, are described and modeled. Small-signal equivalent circuit of ultra-thin body and thin buried oxide and fin field effect transistor (FinFET) are extracted, and their radio frequency figures of merit as well as their advantages and limitations are presented. We demonstrate the importance of performing wideband characterization at the early stage of the technology development in order to identify the device weaknesses and come up with technological solutions to overcome those. With the ongoing downscaling of the metal-oxide-semiconductor devices, the surrounding of the transistor, that is, the contacts, the access lines, and the substrate, starts to play a major role on the transistor behavior. There is an urgent need to develop adequate models for the new generation of devices valid over a wide frequency band.

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Section: Self‐heating Effectssupporting

confidence: 86%

Section: Self‐heating Effectsmentioning

confidence: 99%

Silicon‐on‐insulator MOSFETs models in analog/RF domain

Raskin

2013

Int J Numerical Modelling

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“…Figure 1 provides a simple sketch of the simulated planar devices and fin-FETs; Table 1 summarizes the values assumed for the most important device parameters. 31 The simulation domain is 14 mm wide in the direction along the channel; we have performed simulations featuring 8 and 20 mm wide domains as well, and we have found that the differences in terms of obtained current and temperature are less than 1%. This trend is common to all the considered structures, and shows that the simulation domain adopted does not impact the results.…”

Section: Comparative Analysis Of She In Different Soi Architecturesmentioning

confidence: 91%

Simulation of Self‐Heating Effects in Different SOI MOS Architectures

Luryi

Zaslavsky

2010

Future Trends in Microelectronics

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Self-heating effects (SHEs) are expected to become an increasing problem for future technological nodes, due to the use of new architectures such as silicon-on-insulator (SOI). Thin silicon layers have a much lower thermal conductivity than bulk silicon [1]; moreover, in SOI devices the channel is thermally insulated from the underlying substrate by a SiO 2 buried-oxide layer. All these aspects cause severe SHE, that detrimentally impacts the carrier mobility and therefore the saturation drain current I DS .We discuss SHE in different SOI architectures: n-channel planar single-gate (SG), double-gate (DG), and FinFET transistors, designed to have the same electrical isothermal characteristics, e.g. same threshold voltage, transconductance, and a good immunity from short-channel-effects (SCEs).The DG and FinFET transistors feature the same silicon thickness (t Si = W fin = 10 nm) and gate length (L G = 50 nm); as the SG device is strongly affected by SCE, we considered two different scenarios: t Si = 10 nm and L G = 64 nm, or t Si = 5nm and L G = 50 nm.Our analysis used a commercial 3D electro-thermal simulator, with a temperature-and film thicknessdependent model for the silicon thermal conductivity adopted from [2]. As the standard drift-diffusion approach is unable to account for nonequilibrium phenomena in ultrashort devices, and therefore underestimates I DS , the mobility parameters have been modified to match Monte Carlo-calculated I DS -V DS curves [3]. Different solutions for the thermal boundary conditions have been studied.The simulations pointed out that the SHE detrimentally impacts the device performance, and it is dependent on the device structure. In particular, the thermal resistance due to the source/ drain access regions, as well as the ratio between the surface available for the heat dissipation through the buried oxide and the volume of the active region, change from a structure to another. FIG. 1. Transfer characteristics at V D = 1.0 V (a) and output characteristics at V G =1.0 V (b) calculated by 3D electro-thermal simulations; the gate and S/D contacts are treated as adiabatic.

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“…3D electro-thermal simulation demands a huge simulation time, we restrict the representation of the devices in two dimensions (2D), for the present study. This approach represents the worst case in terms of device self-heating, because the contribution to cooling from heat dissipation in the direction of device width is being neglected [10].…”

Section: Simulation Methodsmentioning

confidence: 99%

Self-heating effects in analog Bulk and SOI CMOS circuits

Roy

Sangiorgi

Fiegna

2010

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

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In this work, we study the impact of device selfheating on Bulk and double-gate silicon-on-insulator (DGSOI) technologies using self-consistent electrothermal (ET) simulations. Device characteristics of Bulk and DGSOI MOSFETs have been studied to estimate device performance and the impact of self-heating on the same. Self-heating effect (SHE) on the AC performance has also been studied for these two technologies.

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Simulation of self-heating effects in different SOI MOS architectures

Cited by 40 publications

References 15 publications

Silicon‐on‐insulator MOSFETs models in analog/RF domain

Silicon‐on‐insulator MOSFETs models in analog/RF domain

Simulation of Self‐Heating Effects in Different SOI MOS Architectures

Self-heating effects in analog Bulk and SOI CMOS circuits

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