As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance of processors by making the latency of circuits less predictable and thus requiring conservative design approaches. In this paper, we use Monte Carlo simulations in addition to worst-case circuit analysis to establish the overall delay due to process variations in a data cache sub-system under both typical and worst-case conditions. The distribution of the cache critical-path-delay in the typical scenario was determined by performing Monte Carlo simulations at different supply voltages, threshold voltages, and transistor lengths on a complete cache design. In addition to establishing the delay variation, we present an adaptive variable-cycle-latency cache architecture that mitigates the impact of process variations on access latency by closely following the typical latency behavior rather than assuming a conservative worst-case design-point. Simulation results show that our adaptive data cache can achieve a 9% to 31% performance improvement in a superscalar processor, on the SPEC2000 applications studied, compared to a conventional design. The area overhead for the additional circuits of the adaptive technique has less than 1% of the total cache area. Additional performance improvement potential exists in processors where the data cache access is on the critical path, by allowing a more aggressive clock rate.Index Terms-CMOS memory integrated circuits, memory architecture, process variations.
As the transistor feature size becomes smaller, circuits show an increased sensitivity to the fluctuations of process parameters. These variations could severely affect the performance and power consumption of processors. In this paper, we establish what the overall leakage power is due to process variations in a cache and show how power and performance can be managed with the help of an adaptive cache sub-system despite process variation effects. The distribution of the cache leakage power was determined by performing Monte-Carlo simulations at different supply voltages, threshold voltages, and transistor lengths on a complete cache design before and after incorporating leakage optimizations. Simulation results show that our adaptive data cache is process variations resilient and can achieve in average 10% performance improvement on SPEC2000 applications in a superscalar processor, in conjunction with 6X reduction in the mean leakage power compared with a conventional design.
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