Data Memory Subsystem Resilient to Process Variations

Abstract

As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance of processors by making the latency of circuits less predictable and thus requiring conservative design approaches. In this paper, we use Monte Carlo simulations in addition to worst-case circuit analysis to establish the overall delay due to process variations in a data cache sub-system under both typical and worst-case conditions. The distribution of the cache critical-path-delay in the typical scenario was determined by performing Monte Carlo simulations at different supply voltages, threshold voltages, and transistor lengths on a complete cache design. In addition to establishing the delay variation, we present an adaptive variable-cycle-latency cache architecture that mitigates the impact of process variations on access latency by closely following the typical latency behavior rather than assuming a conservative worst-case design-point. Simulation results show that our adaptive data cache can achieve a 9% to 31% performance improvement in a superscalar processor, on the SPEC2000 applications studied, compared to a conventional design. The area overhead for the additional circuits of the adaptive technique has less than 1% of the total cache area. Additional performance improvement potential exists in processors where the data cache access is on the critical path, by allowing a more aggressive clock rate.Index Terms-CMOS memory integrated circuits, memory architecture, process variations.

Asymmetric-access aware optimization for STT-RAM caches with process variations

“…Variable-latency access is an effective method to mitigate the impact of process variations on caches [3,8,11,7]. In a cache using variable-latency access technique, the cache access latency is no longer a fixed value as in a traditional worstcase cache design.…”

“…One variable-latency cache architecture uses a delay storage to record the delay time for each cache line [3]. In another variable-latency cache design, they enabled the variable access cache by modifying the function units and adding special queues to store the dependent instructions [8].…”

“…The organization of FAP and SAP for STT-RAM cache is different from traditional variable-access latency cache structure in prior work [3,8,7]. In prior work, the access latency is identified with a fine granularity, which is a single cache line.…”

“…When the dynamic data allocation is employed, our variablelatency access cache structure can outperform those in prior work for three reasons [3,8,7]. First, data migration is feasible to be realized when there are only SAP and FAP.…”

“…Second, a block remapping is necessary to prevent some cache sets from being significantly affected by process variations. After using our techniques, the experimental results show that the performance can be improved by 13.8% and power consumption can be reduced by 14.1% compared to a prior approach [3].…”