Power and performance tradeoffs with process variation resilient adaptive cache architectures

Abstract

As the transistor feature size becomes smaller, circuits show an increased sensitivity to the fluctuations of process parameters. These variations could severely affect the performance and power consumption of processors. In this paper, we establish what the overall leakage power is due to process variations in a cache and show how power and performance can be managed with the help of an adaptive cache sub-system despite process variation effects. The distribution of the cache leakage power was determined by performing Monte-Carlo simulations at different supply voltages, threshold voltages, and transistor lengths on a complete cache design before and after incorporating leakage optimizations. Simulation results show that our adaptive data cache is process variations resilient and can achieve in average 10% performance improvement on SPEC2000 applications in a superscalar processor, in conjunction with 6X reduction in the mean leakage power compared with a conventional design.

Energy consumption and execution time estimation of embedded system applications

“…Another work [BM08] adopted the SimpleScalar [BA97] architecture simulator in order to extend the cache at the circuit level to allow power and performance trade-offs to be managed. This research divided the power consumption into two components, active power and leakage power.…”